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drm/amd/display: Adding interface to log hw state when underflow happens
[why] Will help us better debug underflow issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Muhammad Ahmed <Muhammad.Ahmed@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Muhammad Ahmed
Alex Deucher
parent
20ea30a793
commit
5dc0ec782e
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@ -6339,3 +6339,21 @@ bool dc_can_clear_cursor_limit(struct dc *dc)
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return false;
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}
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void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,
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struct dc_underflow_debug_data *out_data)
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{
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struct timing_generator *tg = NULL;
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for (int i = 0; i < MAX_PIPES; i++) {
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if (dc->res_pool->timing_generators[i] &&
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dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {
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tg = dc->res_pool->timing_generators[i];
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break;
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}
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}
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dc_exit_ips_for_hw_access(dc);
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if (dc->hwss.get_underflow_debug_data)
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dc->hwss.get_underflow_debug_data(dc, tg, out_data);
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}
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@ -1819,6 +1819,23 @@ struct dc_surface_update {
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struct dc_bias_and_scale bias_and_scale;
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};
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struct dc_underflow_debug_data {
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uint32_t otg_inst;
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uint32_t otg_underflow;
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uint32_t h_position;
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uint32_t v_position;
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uint32_t otg_frame_count;
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struct dc_underflow_per_hubp_debug_data {
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uint32_t hubp_underflow;
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uint32_t hubp_in_blank;
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uint32_t hubp_readline;
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uint32_t det_config_error;
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} hubps[MAX_PIPES];
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uint32_t curr_det_sizes[MAX_PIPES];
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uint32_t target_det_sizes[MAX_PIPES];
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uint32_t compbuf_config_error;
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};
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/*
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* Create a new surface with default parameters;
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*/
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@ -2713,4 +2730,17 @@ bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
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bool dc_is_cursor_limit_pending(struct dc *dc);
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bool dc_can_clear_cursor_limit(struct dc *dc);
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/**
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* dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.
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*
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* @dc: Pointer to the display core context.
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* @primary_otg_inst: Instance index of the primary OTG that underflowed.
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* @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information.
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*
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* This function collects and logs underflow-related HW states when underflow happens,
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* including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
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* The results are stored in the provided out_data structure for further analysis or logging.
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*/
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void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);
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#endif /* DC_INTERFACE_H_ */
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@ -440,6 +440,35 @@ void hubbub3_init_watermarks(struct hubbub *hubbub)
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REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
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}
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void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0],
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DET0_SIZE, &target_det_sizes[0]);
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REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1],
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DET1_SIZE, &target_det_sizes[1]);
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REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2],
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DET2_SIZE, &target_det_sizes[2]);
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REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3],
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DET3_SIZE, &target_det_sizes[3]);
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}
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uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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uint32_t compbuf_config_error = 0;
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REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR,
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&compbuf_config_error);
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return compbuf_config_error;
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}
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static const struct hubbub_funcs hubbub30_funcs = {
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.update_dchub = hubbub2_update_dchub,
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.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
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@ -457,6 +486,8 @@ static const struct hubbub_funcs hubbub30_funcs = {
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.force_pstate_change_control = hubbub3_force_pstate_change_control,
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.init_watermarks = hubbub3_init_watermarks,
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.hubbub_read_state = hubbub2_read_state,
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.get_det_sizes = hubbub3_get_det_sizes,
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.compbuf_config_error = hubbub3_compbuf_config_error,
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};
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void hubbub3_construct(struct dcn20_hubbub *hubbub3,
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@ -133,4 +133,10 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
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void hubbub3_init_watermarks(struct hubbub *hubbub);
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void hubbub3_get_det_sizes(struct hubbub *hubbub,
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uint32_t *curr_det_sizes,
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uint32_t *target_det_sizes);
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uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub);
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#endif
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@ -1071,6 +1071,8 @@ static const struct hubbub_funcs hubbub31_funcs = {
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.program_compbuf_size = dcn31_program_compbuf_size,
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.init_crb = dcn31_init_crb,
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.hubbub_read_state = hubbub2_read_state,
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.get_det_sizes = hubbub3_get_det_sizes,
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.compbuf_config_error = hubbub3_compbuf_config_error,
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};
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void hubbub31_construct(struct dcn20_hubbub *hubbub31,
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@ -1009,6 +1009,8 @@ static const struct hubbub_funcs hubbub32_funcs = {
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.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
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.set_request_limit = hubbub32_set_request_limit,
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.get_mall_en = hubbub32_get_mall_en,
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.get_det_sizes = hubbub3_get_det_sizes,
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.compbuf_config_error = hubbub3_compbuf_config_error,
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};
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void hubbub32_construct(struct dcn20_hubbub *hubbub2,
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@ -589,6 +589,8 @@ static const struct hubbub_funcs hubbub35_funcs = {
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.hubbub_read_state = hubbub2_read_state,
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.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
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.dchubbub_init = hubbub35_init,
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.get_det_sizes = hubbub3_get_det_sizes,
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.compbuf_config_error = hubbub3_compbuf_config_error,
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};
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void hubbub35_construct(struct dcn20_hubbub *hubbub2,
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@ -1247,6 +1247,8 @@ static const struct hubbub_funcs hubbub4_01_funcs = {
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.program_compbuf_segments = dcn401_program_compbuf_segments,
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.wait_for_det_update = dcn401_wait_for_det_update,
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.program_arbiter = dcn401_program_arbiter,
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.get_det_sizes = hubbub3_get_det_sizes,
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.compbuf_config_error = hubbub3_compbuf_config_error,
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};
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void hubbub401_construct(struct dcn20_hubbub *hubbub2,
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@ -104,7 +104,8 @@
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SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
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SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
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SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
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SRI(HUBP_CLK_CNTL, HUBP, id)
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SRI(HUBP_CLK_CNTL, HUBP, id),\
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SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
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/* Register address initialization macro for ASICs with VM */
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#define HUBP_REG_LIST_DCN_VM(id)\
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@ -249,7 +250,8 @@
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uint32_t CURSOR_POSITION; \
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uint32_t CURSOR_HOT_SPOT; \
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uint32_t CURSOR_DST_OFFSET; \
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uint32_t HUBP_CLK_CNTL
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uint32_t HUBP_CLK_CNTL; \
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uint32_t HUBPRET_READ_LINE_VALUE
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#define HUBP_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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@ -622,6 +624,8 @@
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
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type PIPE_READ_LINE;\
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type HUBP_SEG_ALLOC_ERR_STATUS;\
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/* todo: get these from GVM instead of reading registers ourselves */\
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type PAGE_DIRECTORY_ENTRY_HI32;\
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type PAGE_DIRECTORY_ENTRY_LO32;\
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@ -505,6 +505,30 @@ void hubp3_init(struct hubp *hubp)
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hubp_reset(hubp);
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}
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uint32_t hubp3_get_current_read_line(struct hubp *hubp)
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{
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uint32_t read_line = 0;
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_GET(HUBPRET_READ_LINE_VALUE,
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PIPE_READ_LINE,
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&read_line);
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return read_line;
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}
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unsigned int hubp3_get_underflow_status(struct hubp *hubp)
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{
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uint32_t hubp_underflow = 0;
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_GET(DCHUBP_CNTL,
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HUBP_UNDERFLOW_STATUS,
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&hubp_underflow);
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return hubp_underflow;
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}
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static struct hubp_funcs dcn30_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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@ -534,6 +558,8 @@ static struct hubp_funcs dcn30_hubp_funcs = {
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.hubp_soft_reset = hubp1_soft_reset,
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.hubp_set_flip_int = hubp1_set_flip_int,
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.hubp_clear_tiling = hubp3_clear_tiling,
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.hubp_get_underflow_status = hubp3_get_underflow_status,
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.hubp_get_current_read_line = hubp3_get_current_read_line,
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};
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bool hubp3_construct(
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@ -243,7 +243,8 @@
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HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
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HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
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HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
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HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
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HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh)
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bool hubp3_construct(
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struct dcn20_hubp *hubp2,
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@ -299,6 +300,11 @@ void hubp3_init(struct hubp *hubp);
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void hubp3_clear_tiling(struct hubp *hubp);
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uint32_t hubp3_get_current_read_line(struct hubp *hubp);
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uint32_t hubp3_get_underflow_status(struct hubp *hubp);
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#endif /* __DC_HUBP_DCN30_H__ */
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@ -68,6 +68,18 @@ void hubp31_program_extended_blank_value(
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hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);
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}
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uint32_t hubp31_get_det_config_error(struct hubp *hubp)
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{
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uint32_t config_error = 0;
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_GET(DCHUBP_CNTL,
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HUBP_SEG_ALLOC_ERR_STATUS,
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&config_error);
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return config_error;
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}
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static struct hubp_funcs dcn31_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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@ -98,6 +110,9 @@ static struct hubp_funcs dcn31_hubp_funcs = {
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.hubp_in_blank = hubp1_in_blank,
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.program_extended_blank = hubp31_program_extended_blank,
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.hubp_clear_tiling = hubp3_clear_tiling,
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.hubp_get_underflow_status = hubp3_get_underflow_status,
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.hubp_get_current_read_line = hubp3_get_current_read_line,
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.hubp_get_det_config_error = hubp31_get_det_config_error,
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};
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bool hubp31_construct(
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@ -228,7 +228,9 @@
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HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
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HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
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HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
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HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
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HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
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bool hubp31_construct(
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@ -246,4 +248,6 @@ void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
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void hubp31_program_extended_blank_value(
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struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);
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uint32_t hubp31_get_det_config_error(struct hubp *hubp);
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#endif /* __DC_HUBP_DCN31_H__ */
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@ -206,6 +206,9 @@ static struct hubp_funcs dcn32_hubp_funcs = {
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.hubp_update_mall_sel = hubp32_update_mall_sel,
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.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
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.hubp_clear_tiling = hubp3_clear_tiling,
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.hubp_get_underflow_status = hubp3_get_underflow_status,
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.hubp_get_current_read_line = hubp3_get_current_read_line,
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.hubp_get_det_config_error = hubp31_get_det_config_error,
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};
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bool hubp32_construct(
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@ -218,6 +218,9 @@ static struct hubp_funcs dcn35_hubp_funcs = {
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.hubp_in_blank = hubp1_in_blank,
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.program_extended_blank = hubp31_program_extended_blank_value,
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.hubp_clear_tiling = hubp3_clear_tiling,
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.hubp_get_underflow_status = hubp3_get_underflow_status,
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.hubp_get_current_read_line = hubp3_get_current_read_line,
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.hubp_get_det_config_error = hubp31_get_det_config_error,
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};
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bool hubp35_construct(
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@ -1071,6 +1071,9 @@ static struct hubp_funcs dcn401_hubp_funcs = {
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.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
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.hubp_clear_tiling = hubp401_clear_tiling,
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.hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,
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.hubp_get_underflow_status = hubp3_get_underflow_status,
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.hubp_get_current_read_line = hubp3_get_current_read_line,
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.hubp_get_det_config_error = hubp31_get_det_config_error,
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};
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bool hubp401_construct(
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@ -252,7 +252,9 @@
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HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P0, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P0, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P1, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh)
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HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh),\
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HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
|
||||
|
||||
void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
|
||||
|
||||
|
|
|
|||
|
|
@ -1228,3 +1228,51 @@ void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
void dcn30_get_underflow_debug_data(const struct dc *dc,
|
||||
struct timing_generator *tg,
|
||||
struct dc_underflow_debug_data *out_data)
|
||||
{
|
||||
struct hubbub *hubbub = dc->res_pool->hubbub;
|
||||
|
||||
if (tg) {
|
||||
uint32_t v_blank_start = 0, v_blank_end = 0;
|
||||
|
||||
out_data->otg_inst = tg->inst;
|
||||
|
||||
tg->funcs->get_scanoutpos(tg,
|
||||
&v_blank_start,
|
||||
&v_blank_end,
|
||||
&out_data->h_position,
|
||||
&out_data->v_position);
|
||||
|
||||
out_data->otg_frame_count = tg->funcs->get_frame_count(tg);
|
||||
|
||||
out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg);
|
||||
}
|
||||
|
||||
for (int i = 0; i < MAX_PIPES; i++) {
|
||||
struct hubp *hubp = dc->res_pool->hubps[i];
|
||||
|
||||
if (hubp) {
|
||||
if (hubp->funcs->hubp_get_underflow_status)
|
||||
out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp);
|
||||
|
||||
if (hubp->funcs->hubp_in_blank)
|
||||
out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp);
|
||||
|
||||
if (hubp->funcs->hubp_get_current_read_line)
|
||||
out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp);
|
||||
|
||||
if (hubp->funcs->hubp_get_det_config_error)
|
||||
out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp);
|
||||
}
|
||||
}
|
||||
|
||||
if (hubbub->funcs->get_det_sizes)
|
||||
hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes);
|
||||
|
||||
if (hubbub->funcs->compbuf_config_error)
|
||||
out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub);
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include "hw_sequencer_private.h"
|
||||
|
||||
struct dc;
|
||||
struct dc_underflow_debug_data;
|
||||
|
||||
void dcn30_init_hw(struct dc *dc);
|
||||
void dcn30_program_all_writeback_pipes_in_tree(
|
||||
|
|
@ -98,4 +99,8 @@ void dcn30_prepare_bandwidth(struct dc *dc,
|
|||
|
||||
void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);
|
||||
|
||||
void dcn30_get_underflow_debug_data(const struct dc *dc,
|
||||
struct timing_generator *tg,
|
||||
struct dc_underflow_debug_data *out_data);
|
||||
|
||||
#endif /* __DC_HWSS_DCN30_H__ */
|
||||
|
|
|
|||
|
|
@ -110,6 +110,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
|
|||
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
|
||||
.is_abm_supported = dcn21_is_abm_supported,
|
||||
.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn30_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -112,6 +112,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
|
|||
.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
|
||||
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
|
||||
.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn31_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
|
|||
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
|
||||
.calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider,
|
||||
.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn314_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
|
|||
.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
|
||||
.program_outstanding_updates = dcn32_program_outstanding_updates,
|
||||
.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn32_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -128,6 +128,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
|
|||
.enable_plane = dcn20_enable_plane,
|
||||
.update_dchubp_dpp = dcn20_update_dchubp_dpp,
|
||||
.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn35_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -123,6 +123,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
|
|||
.set_long_vtotal = dcn35_set_long_vblank,
|
||||
.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
|
||||
.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn351_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -104,6 +104,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
|
|||
.enable_plane = dcn20_enable_plane,
|
||||
.update_dchubp_dpp = dcn20_update_dchubp_dpp,
|
||||
.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
|
||||
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn401_private_funcs = {
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ struct link_resource;
|
|||
struct dc_dmub_cmd;
|
||||
struct pg_block_update;
|
||||
struct drr_params;
|
||||
struct dc_underflow_debug_data;
|
||||
|
||||
struct subvp_pipe_control_lock_fast_params {
|
||||
struct dc *dc;
|
||||
|
|
@ -475,6 +476,9 @@ struct hw_sequencer_funcs {
|
|||
struct dc_state *context);
|
||||
void (*post_unlock_reset_opp)(struct dc *dc,
|
||||
struct pipe_ctx *opp_head);
|
||||
void (*get_underflow_debug_data)(const struct dc *dc,
|
||||
struct timing_generator *tg,
|
||||
struct dc_underflow_debug_data *out_data);
|
||||
};
|
||||
|
||||
void color_space_to_black_color(
|
||||
|
|
|
|||
|
|
@ -229,6 +229,8 @@ struct hubbub_funcs {
|
|||
void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
|
||||
void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst);
|
||||
bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);
|
||||
void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes);
|
||||
uint32_t (*compbuf_config_error)(struct hubbub *hubbub);
|
||||
};
|
||||
|
||||
struct hubbub {
|
||||
|
|
|
|||
|
|
@ -306,6 +306,8 @@ struct hubp_funcs {
|
|||
int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
|
||||
void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
|
||||
void (*hubp_clear_tiling)(struct hubp *hubp);
|
||||
uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);
|
||||
uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1141,7 +1141,8 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
|
|||
SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \
|
||||
SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \
|
||||
SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \
|
||||
SRI_ARR(HUBP_CLK_CNTL, HUBP, id)
|
||||
SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \
|
||||
SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
|
||||
#define HUBP_REG_LIST_DCN2_COMMON_RI(id) \
|
||||
HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id), \
|
||||
SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \
|
||||
|
|
|
|||
|
|
@ -140,7 +140,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
|
|||
SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \
|
||||
HUBP_3DLUT_FL_REG_LIST_DCN401(id), \
|
||||
SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \
|
||||
SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id)
|
||||
SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id), \
|
||||
SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
|
||||
|
||||
/* ABM */
|
||||
#define ABM_DCN401_REG_LIST_RI(id) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user