github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-31 02:24:24 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

RISC-V: Add defines for the SBI nested acceleration extension

Browse Source 
Add defines for the new SBI nested acceleration extension which was
ratified as part of the SBI v2.0 specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-8-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel 2024-10-21 01:17:28 +05:30 committed by Anup Patel
parent 15ff2ff3c3
commit 5daf89e73d
1 changed files with 120 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
arch/riscv/include/asm/sbi.h
View File

@ -34,6 +34,7 @@ enum sbi_ext_id {
SBI_EXT_PMU = 0x504D55,
SBI_EXT_DBCN = 0x4442434E,
SBI_EXT_STA = 0x535441,
SBI_EXT_NACL = 0x4E41434C,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@ -281,6 +282,125 @@ struct sbi_sta_struct {
#define SBI_SHMEM_DISABLE -1
enum sbi_ext_nacl_fid {
SBI_EXT_NACL_PROBE_FEATURE = 0x0,
SBI_EXT_NACL_SET_SHMEM = 0x1,
SBI_EXT_NACL_SYNC_CSR = 0x2,
SBI_EXT_NACL_SYNC_HFENCE = 0x3,
SBI_EXT_NACL_SYNC_SRET = 0x4,
};
enum sbi_ext_nacl_feature {
SBI_NACL_FEAT_SYNC_CSR = 0x0,
SBI_NACL_FEAT_SYNC_HFENCE = 0x1,
SBI_NACL_FEAT_SYNC_SRET = 0x2,
SBI_NACL_FEAT_AUTOSWAP_CSR = 0x3,
};
#define SBI_NACL_SHMEM_ADDR_SHIFT 12
#define SBI_NACL_SHMEM_SCRATCH_OFFSET 0x0000
#define SBI_NACL_SHMEM_SCRATCH_SIZE 0x1000
#define SBI_NACL_SHMEM_SRET_OFFSET 0x0000
#define SBI_NACL_SHMEM_SRET_SIZE 0x0200
#define SBI_NACL_SHMEM_AUTOSWAP_OFFSET (SBI_NACL_SHMEM_SRET_OFFSET + \
SBI_NACL_SHMEM_SRET_SIZE)
#define SBI_NACL_SHMEM_AUTOSWAP_SIZE 0x0080
#define SBI_NACL_SHMEM_UNUSED_OFFSET (SBI_NACL_SHMEM_AUTOSWAP_OFFSET + \
SBI_NACL_SHMEM_AUTOSWAP_SIZE)
#define SBI_NACL_SHMEM_UNUSED_SIZE 0x0580
#define SBI_NACL_SHMEM_HFENCE_OFFSET (SBI_NACL_SHMEM_UNUSED_OFFSET + \
SBI_NACL_SHMEM_UNUSED_SIZE)
#define SBI_NACL_SHMEM_HFENCE_SIZE 0x0780
#define SBI_NACL_SHMEM_DBITMAP_OFFSET (SBI_NACL_SHMEM_HFENCE_OFFSET + \
SBI_NACL_SHMEM_HFENCE_SIZE)
#define SBI_NACL_SHMEM_DBITMAP_SIZE 0x0080
#define SBI_NACL_SHMEM_CSR_OFFSET (SBI_NACL_SHMEM_DBITMAP_OFFSET + \
SBI_NACL_SHMEM_DBITMAP_SIZE)
#define SBI_NACL_SHMEM_CSR_SIZE ((__riscv_xlen / 8) * 1024)
#define SBI_NACL_SHMEM_SIZE (SBI_NACL_SHMEM_CSR_OFFSET + \
SBI_NACL_SHMEM_CSR_SIZE)
#define SBI_NACL_SHMEM_CSR_INDEX(__csr_num) \
((((__csr_num) & 0xc00) >> 2) | ((__csr_num) & 0xff))
#define SBI_NACL_SHMEM_HFENCE_ENTRY_SZ ((__riscv_xlen / 8) * 4)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_MAX \
(SBI_NACL_SHMEM_HFENCE_SIZE / \
SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
#define SBI_NACL_SHMEM_HFENCE_ENTRY(__num) \
(SBI_NACL_SHMEM_HFENCE_OFFSET + \
(__num) * SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(__num) \
SBI_NACL_SHMEM_HFENCE_ENTRY(__num)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(__num)\
(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + (__riscv_xlen / 8))
#define SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(__num)\
(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + \
((__riscv_xlen / 8) * 3))
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS 1
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT \
(__riscv_xlen - SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND \
(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK << \
SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS 3
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS 4
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA 0x0
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL 0x1
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID 0x2
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL 0x3
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA 0x4
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL 0x5
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID 0x6
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL 0x7
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS 1
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS 7
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_ORDER_BASE 12
#if __riscv_xlen == 32
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 9
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 7
#else
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 16
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 14
#endif
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT \
SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS) - 1)
#define SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS BIT(0)
#define SBI_NACL_SHMEM_AUTOSWAP_HSTATUS ((__riscv_xlen / 8) * 1)
#define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
#define SBI_NACL_SHMEM_SRET_X_LAST 31
/* SBI spec version fields */
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24