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drm/amd/display: Clamp VStartup value at DML calculations time
[why] Some timings with a large VBlank cause the value to overflow the register related, while also producing other wrong values in DML output. [how] Clamp VStartup at the DCN3.1 maximum value Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2668,6 +2668,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
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(double) v->WritebackDelay[v->VoltageLevel][k]
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/ (v->HTotal[k] / v->PixelClock[k]),
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1));
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if (v->MaxVStartupLines[k] > 1023)
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v->MaxVStartupLines[k] = 1023;
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#ifdef __DML_VBA_DEBUG__
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dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
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@ -5064,6 +5066,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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/ (v->HTotal[k]
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/ v->PixelClock[k]),
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1.0));
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if (v->MaximumVStartup[i][j][k] > 1023)
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v->MaximumVStartup[i][j][k] = 1023;
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v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
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}
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}
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