From 25937d399be2ee9852103a41aaca42d91b140d79 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Oct 2025 18:10:39 +0200 Subject: [PATCH 1/6] dt-bindings: power: Add power domain IDs for Tegra264 Add the set of power domain IDs available on the Tegra264 SoC so that they can be used in device tree files. Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../dt-bindings/power/nvidia,tegra264-bpmp.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/power/nvidia,tegra264-bpmp.h diff --git a/include/dt-bindings/power/nvidia,tegra264-bpmp.h b/include/dt-bindings/power/nvidia,tegra264-bpmp.h new file mode 100644 index 000000000000..2eef4a2a02b0 --- /dev/null +++ b/include/dt-bindings/power/nvidia,tegra264-bpmp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H +#define DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H + +#define TEGRA264_POWER_DOMAIN_DISP 1 +#define TEGRA264_POWER_DOMAIN_AUD 2 +/* reserved 3:9 */ +#define TEGRA264_POWER_DOMAIN_XUSB_SS 10 +#define TEGRA264_POWER_DOMAIN_XUSB_DEV 11 +#define TEGRA264_POWER_DOMAIN_XUSB_HOST 12 +#define TEGRA264_POWER_DOMAIN_MGBE0 13 +#define TEGRA264_POWER_DOMAIN_MGBE1 14 +#define TEGRA264_POWER_DOMAIN_MGBE2 15 +#define TEGRA264_POWER_DOMAIN_MGBE3 16 +#define TEGRA264_POWER_DOMAIN_VI 17 +#define TEGRA264_POWER_DOMAIN_VIC 18 +#define TEGRA264_POWER_DOMAIN_ISP0 19 +#define TEGRA264_POWER_DOMAIN_ISP1 20 +#define TEGRA264_POWER_DOMAIN_PVA0 21 +#define TEGRA264_POWER_DOMAIN_GPU 22 + +#endif /* DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H */ From ccec1069246ad121c1cbb6494d75140d512a9b5b Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Wed, 11 Jun 2025 13:53:37 -0500 Subject: [PATCH 2/6] dt-bindings: arm: tegra: Document Jetson Nano Devkits Add compatibles for the Tegra210 Jetson Nano Developer Kits Signed-off-by: Aaron Kling Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 6139407c2cbf..50a31dba7bec 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -189,6 +189,11 @@ properties: - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2894-0050-a08 + - nvidia,p3450-0000 + - const: nvidia,tegra210 + - items: + - const: nvidia,p3541-0000 + - const: nvidia,p3450-0000 - const: nvidia,tegra210 - description: Jetson TX2 Developer Kit items: From a0c70244e5a877be917fc6aaf1e58a4debd99c4d Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 16 Oct 2025 10:41:49 +0300 Subject: [PATCH 3/6] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+ The current EPP, ISP and MPE schemas are largely compatible with Tegra114+, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra114-tsec.yaml | 68 +++++++++++++++++++ .../display/tegra/nvidia,tegra20-epp.yaml | 14 ++-- .../display/tegra/nvidia,tegra20-isp.yaml | 15 ++-- .../display/tegra/nvidia,tegra20-mpe.yaml | 18 +++-- 4 files changed, 102 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml new file mode 100644 index 000000000000..2c4d519a1bb7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel + - Thierry Reding + +description: Tegra Security co-processor, an embedded security processor used + mainly to manage the HDCP encryption and keys on the HDMI link. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra114-tsec + - nvidia,tegra124-tsec + - nvidia,tegra210-tsec + + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +examples: + - | + #include + #include + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml index 3c095a5491fe..334f5531b243 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -15,10 +15,16 @@ properties: pattern: "^epp@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + - nvidia,tegra124-epp + + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml index 3bc3b22e98e1..ee25b5e6f1a2 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -12,10 +12,17 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra114-isp + - nvidia,tegra124-isp + - nvidia,tegra210-isp + + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml index 2cd3e60cd0a8..36b76fa8f525 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -12,13 +12,21 @@ maintainers: properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-msenc + - nvidia,tegra124-msenc + + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc reg: maxItems: 1 From e7dc9c3a6fc46e2530119b7c1d174fa9af2b6acb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:49:28 +0300 Subject: [PATCH 4/6] dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI Document CSI HW block found in Tegra20 and Tegra30 SoC. The #nvidia,mipi-calibrate-cells is not an introduction of property, such property already exists in nvidia,tegra114-mipi.yaml and is used in multiple device trees. In case of Tegra30 and Tegra20 CSI block combines mipi calibration function and CSI function, in Tegra114+ mipi calibration got a dedicated hardware block which is already supported. This property here is used to align with mipi-calibration logic used by Tegra114+. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-csi.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml new file mode 100644 index 000000000000..a1aea9590769 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 CSI controller + +maintainers: + - Svyatoslav Ryhel + +properties: + compatible: + enum: + - nvidia,tegra20-csi + - nvidia,tegra30-csi + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia-pad + - const: csib-pad + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: + The number of cells in a MIPI calibration specifier. Should be 1. + The single cell specifies an id of the pad that need to be + calibrated for a given device. Valid pad ids for receiver would be + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: channel 0 represents CSI-A and 1 represents CSI-B + additionalProperties: false + + properties: + reg: + maximum: 1 + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pad is used by this CSI channel and needs to be calibrated. + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: port receiving the video stream from the sensor + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: port sending the video stream to the VI + + required: + - reg + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-csi + then: + properties: + clocks: + maxItems: 1 + + clock-names: false + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-csi + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - power-domains + - "#address-cells" + - "#size-cells" + +# see nvidia,tegra20-vi.yaml for an example From 22c788aec2efc80d6c8f4e8fa00c5a4fb10f8956 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 21 Oct 2025 22:09:26 -0500 Subject: [PATCH 5/6] dt-bindings: devfreq: tegra30-actmon: Add Tegra124 fallback for Tegra210 The Tegra210 actmon is compatible with the existing Tegra124 driver. Describe the compatibles as such. Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- .../bindings/devfreq/nvidia,tegra30-actmon.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml index e3379d106728..ea1dc86bc31f 100644 --- a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml +++ b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml @@ -19,11 +19,14 @@ description: | properties: compatible: - enum: - - nvidia,tegra30-actmon - - nvidia,tegra114-actmon - - nvidia,tegra124-actmon - - nvidia,tegra210-actmon + oneOf: + - enum: + - nvidia,tegra30-actmon + - nvidia,tegra114-actmon + - nvidia,tegra124-actmon + - items: + - const: nvidia,tegra210-actmon + - const: nvidia,tegra124-actmon reg: maxItems: 1 From 905f0dcc38f8078f0641c5cf855f420d78f10ea7 Mon Sep 17 00:00:00 2001 From: Haotien Hsu Date: Mon, 11 Aug 2025 15:45:55 +0800 Subject: [PATCH 6/6] dt-bindings: usb: Add wake-up support for Tegra234 XUSB host controller Populate USB wake events for Tegra234 XUSB host controller. These wake-up events are optional to maintain backward compatibility and because the USB controller does not require them for normal operation. Signed-off-by: Haotien Hsu Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../bindings/usb/nvidia,tegra234-xusb.yaml | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml index db761dcbf72a..ec0993497fbb 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml @@ -32,9 +32,35 @@ properties: - const: bar2 interrupts: + minItems: 2 items: - description: xHCI host interrupt - description: mailbox interrupt + - description: USB wake event 0 + - description: USB wake event 1 + - description: USB wake event 2 + - description: USB wake event 3 + - description: USB wake event 4 + - description: USB wake event 5 + - description: USB wake event 6 + description: | + The first two interrupts are required for the USB host controller. The + remaining USB wake event interrupts are optional. Each USB wake event is + independent; it is not necessary to use all of these events on a + platform. The USB host controller can function even if no wake-up events + are defined. The USB wake event interrupts are handled by the Tegra PMC; + hence, the interrupt controller for these is the PMC and the interrupt + IDs correspond to the PMC wake event IDs. A complete list of wake event + IDs is provided below, and this information is also present in the Tegra + TRM document. + + PMC wake-up 76 for USB3 port 0 wakeup + PMC wake-up 77 for USB3 port 1 wakeup + PMC wake-up 78 for USB3 port 2 and port 3 wakeup + PMC wake-up 79 for USB2 port 0 wakeup + PMC wake-up 80 for USB2 port 1 wakeup + PMC wake-up 81 for USB2 port 2 wakeup + PMC wake-up 82 for USB2 port 3 wakeup clocks: items: @@ -127,8 +153,9 @@ examples: <0x03650000 0x10000>; reg-names = "hcd", "fpci", "bar2"; - interrupts = , - ; + interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>,