github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-07 06:17:02 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

dt-bindings: clock: qcom: Add Hawi CAMCC compatible strings

Browse Source 
The Hawi SoC is a derivative of Kaanapali  with an updated camera
clock controller (CAMCC). While the overall block structure is
similar, Hawi's CAMCC differs from Kaanapali in the following ways:

  - Uses Taycan EHA-T PLLs instead of Taycan EKO-T PLLs, with an
    additional ninth PLL (PLL8)
  - Adds a SQPF block with its own GDSC, AHB clock, and BCR reset
  - Adds a CX GDSC (CAM_CC_TITAN_TOP_CX_GDSC) for the camera subsystem
  - Expands ICP from one to two instances (ICP_0 and ICP_1)

Due to these differences, Hawi requires its own 'qcom,hawi-camcc'
compatible string and a dedicated driver.

The BIST MCLK clock controller (CAMBISTMCLKCC) is unchanged between
Hawi and Kaanapali, allowing the existing Kaanapali CAMBISTMCLKCC
driver to support both SoCs without modification.

Add the 'qcom,hawi-camcc' and 'qcom,hawi-cambistmclkcc' compatible
strings to the binding, along with the corresponding clock ID header.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
Link: https://patch.msgid.link/20260915-camcc-hawi-v3-1-5b57f45477f1@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
This commit is contained in:
Vivek Aknurwar 2026-09-15 10:33:01 -07:00 committed by Bjorn Andersson
parent cee9395acd
commit 5cea6b0bbf
2 changed files with 197 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -16,6 +16,7 @@ description: |
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,hawi-camcc.h
include/dt-bindings/clock/qcom,kaanapali-camcc.h
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
@ -26,15 +27,21 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
oneOf:
- enum:
- qcom,hawi-camcc
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
- items:
- enum:
- qcom,hawi-cambistmclkcc
- const: qcom,kaanapali-cambistmclkcc
clocks:
items:
@ -43,6 +50,10 @@ properties:
- description: Board active XO source
- description: Sleep clock source
interconnects:
items:
- description: Interconnect path to enable the MultiMedia NoC
power-domains:
description:
Power domains required for the clock controller to operate
@ -78,12 +89,22 @@ allOf:
then:
required:
- required-opps
- if:
properties:
compatible:
contains:
const: qcom,hawi-camcc
then:
required:
- interconnects
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ade0000 {
@ -97,6 +118,8 @@ examples:
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

165
include/dt-bindings/clock/qcom,hawi-camcc.h Normal file
View File

@ -0,0 +1,165 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_HAWI_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_HAWI_H
/* CAM_CC clocks */
#define CAM_CC_CAM_TOP_AHB_CLK 0
#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1
#define CAM_CC_CAMNOC_DCD_XO_CLK 2
#define CAM_CC_CAMNOC_NRT_AXI_CLK 3
#define CAM_CC_CAMNOC_NRT_CRE_CLK 4
#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5
#define CAM_CC_CAMNOC_NRT_IPE_SCALERS_CLK 6
#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 7
#define CAM_CC_CAMNOC_NRT_SQPF_CLK 8
#define CAM_CC_CAMNOC_RT_AXI_CLK 9
#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10
#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11
#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 12
#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 13
#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 14
#define CAM_CC_CCI_0_CLK 15
#define CAM_CC_CCI_0_CLK_SRC 16
#define CAM_CC_CCI_1_CLK 17
#define CAM_CC_CCI_1_CLK_SRC 18
#define CAM_CC_CCI_2_CLK 19
#define CAM_CC_CCI_2_CLK_SRC 20
#define CAM_CC_CORE_AHB_CLK 21
#define CAM_CC_CPHY_RX_CLK_SRC 22
#define CAM_CC_CRE_AHB_CLK 23
#define CAM_CC_CRE_CLK 24
#define CAM_CC_CRE_CLK_SRC 25
#define CAM_CC_CSI0PHYTIMER_CLK 26
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
#define CAM_CC_CSI1PHYTIMER_CLK 28
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
#define CAM_CC_CSI2PHYTIMER_CLK 30
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI3PHYTIMER_CLK 32
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
#define CAM_CC_CSI4PHYTIMER_CLK 34
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI5PHYTIMER_CLK 36
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 37
#define CAM_CC_CSID_CLK 38
#define CAM_CC_CSID_CLK_SRC 39
#define CAM_CC_CSID_CSIPHY_RX_CLK 40
#define CAM_CC_CSIPHY0_CLK 41
#define CAM_CC_CSIPHY1_CLK 42
#define CAM_CC_CSIPHY2_CLK 43
#define CAM_CC_CSIPHY3_CLK 44
#define CAM_CC_CSIPHY4_CLK 45
#define CAM_CC_CSIPHY5_CLK 46
#define CAM_CC_CX_GDSC_CLK 47
#define CAM_CC_DRV_AHB_CLK 48
#define CAM_CC_DRV_XO_CLK 49
#define CAM_CC_FAST_AHB_CLK_SRC 50
#define CAM_CC_GDSC_CLK 51
#define CAM_CC_ICP_0_AHB_CLK 52
#define CAM_CC_ICP_0_CLK 53
#define CAM_CC_ICP_0_CLK_SRC 54
#define CAM_CC_ICP_1_AHB_CLK 55
#define CAM_CC_ICP_1_CLK 56
#define CAM_CC_ICP_1_CLK_SRC 57
#define CAM_CC_IFE_LITE_AHB_CLK 58
#define CAM_CC_IFE_LITE_CLK 59
#define CAM_CC_IFE_LITE_CLK_SRC 60
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 61
#define CAM_CC_IFE_LITE_CSID_CLK 62
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 63
#define CAM_CC_IPE_NPS_AHB_CLK 64
#define CAM_CC_IPE_NPS_CLK 65
#define CAM_CC_IPE_NPS_CLK_SRC 66
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 67
#define CAM_CC_IPE_PPS_CLK 68
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 69
#define CAM_CC_IPE_SCALERS_CLK 70
#define CAM_CC_IPE_SCALERS_FAST_AHB_CLK 71
#define CAM_CC_JPEG_CLK 72
#define CAM_CC_JPEG_CLK_SRC 73
#define CAM_CC_MMSS_AHB_CLK 74
#define CAM_CC_OFE_AHB_CLK 75
#define CAM_CC_OFE_ANCHOR_CLK 76
#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 77
#define CAM_CC_OFE_CLK_SRC 78
#define CAM_CC_OFE_HDR_CLK 79
#define CAM_CC_OFE_HDR_FAST_AHB_CLK 80
#define CAM_CC_OFE_MAIN_CLK 81
#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 82
#define CAM_CC_OFE_MP_CLK 83
#define CAM_CC_OFE_MP_FAST_AHB_CLK 84
#define CAM_CC_PLL0 85
#define CAM_CC_PLL0_OUT_EVEN 86
#define CAM_CC_PLL0_OUT_ODD 87
#define CAM_CC_PLL1 88
#define CAM_CC_PLL1_OUT_EVEN 89
#define CAM_CC_PLL2 90
#define CAM_CC_PLL2_OUT_EVEN 91
#define CAM_CC_PLL3 92
#define CAM_CC_PLL3_OUT_EVEN 93
#define CAM_CC_PLL4 94
#define CAM_CC_PLL4_OUT_EVEN 95
#define CAM_CC_PLL5 96
#define CAM_CC_PLL5_OUT_EVEN 97
#define CAM_CC_PLL6 98
#define CAM_CC_PLL6_OUT_EVEN 99
#define CAM_CC_PLL6_OUT_ODD 100
#define CAM_CC_PLL7 101
#define CAM_CC_PLL8 102
#define CAM_CC_PLL8_OUT_EVEN 103
#define CAM_CC_QDSS_DEBUG_CLK 104
#define CAM_CC_QDSS_DEBUG_CLK_SRC 105
#define CAM_CC_QDSS_DEBUG_XO_CLK 106
#define CAM_CC_SLEEP_CLK 107
#define CAM_CC_SLOW_AHB_CLK_SRC 108
#define CAM_CC_SQPF_AHB_CLK 109
#define CAM_CC_SQPF_CLK 110
#define CAM_CC_SQPF_CLK_SRC 111
#define CAM_CC_SQPF_FAST_AHB_CLK 112
#define CAM_CC_TFE_0_BAYER_CLK 113
#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 114
#define CAM_CC_TFE_0_CLK_SRC 115
#define CAM_CC_TFE_0_MAIN_CLK 116
#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 117
#define CAM_CC_TFE_1_BAYER_CLK 118
#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 119
#define CAM_CC_TFE_1_CLK_SRC 120
#define CAM_CC_TFE_1_MAIN_CLK 121
#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 122
#define CAM_CC_TFE_2_BAYER_CLK 123
#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 124
#define CAM_CC_TFE_2_CLK_SRC 125
#define CAM_CC_TFE_2_MAIN_CLK 126
#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 127
#define CAM_CC_TITAN_CAMNOC_XO_CLK 128
#define CAM_CC_TITAN_MNOC_HF_CLK 129
#define CAM_CC_TITAN_MNOC_SF_CLK 130
#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK 131
#define CAM_CC_XO_CLK_SRC 132
/* CAM_CC power domains */
#define CAM_CC_IPE_0_GDSC 0
#define CAM_CC_OFE_GDSC 1
#define CAM_CC_SQPF_GDSC 2
#define CAM_CC_TFE_0_GDSC 3
#define CAM_CC_TFE_1_GDSC 4
#define CAM_CC_TFE_2_GDSC 5
#define CAM_CC_TITAN_TOP_CX_GDSC 6
#define CAM_CC_TITAN_TOP_GDSC 7
/* CAM_CC resets */
#define CAM_CC_DRV_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IPE_0_BCR 2
#define CAM_CC_OFE_BCR 3
#define CAM_CC_QDSS_DEBUG_BCR 4
#define CAM_CC_SQPF_BCR 5
#define CAM_CC_TFE_0_BCR 6
#define CAM_CC_TFE_1_BCR 7
#define CAM_CC_TFE_2_BCR 8
#endif