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drm/amd/swsmu: Add new param regs for SMU15

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Some SMU messages have changed to multi reg read/write
Initialize during smu_early_init

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Pratik Vishwakarma 2026-01-28 03:52:03 +00:00 committed by Alex Deucher
parent e98bb71e24
commit 5cc934e089
1 changed files with 9 additions and 1 deletions
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10
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
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@ -52,6 +52,12 @@
#define mmMP1_SMN_C2PMSG_32 0x0060
#define mmMP1_SMN_C2PMSG_32_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_33 0x0061
#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_34 0x0062
#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1
/* MALLPowerController message arguments (Defines for the Cache mode control) */
#define SMU_MALL_PMFW_CONTROL 0
#define SMU_MALL_DRIVER_CONTROL 1
@ -1347,7 +1353,9 @@ static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu)
ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30);
ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31);
ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32);
ctl->config.num_arg_regs = 1;
ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_33);
ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_34);
ctl->config.num_arg_regs = 3;
ctl->ops = &smu_msg_v1_ops;
ctl->default_timeout = adev->usec_timeout * 20;
ctl->message_map = smu_v15_0_0_message_map;