arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
to the analog block routing channel. Update the xo_board_clk nodes in
the board DTS files to use clock-div/clock-mult accordingly.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
George Moussalem 2025-07-21 10:04:36 +04:00 committed by Bjorn Andersson
parent c006b249c5
commit 5ca3d42384
3 changed files with 6 additions and 3 deletions

View File

@ -120,5 +120,6 @@ &usbphy0 {
};
&xo_board_clk {
clock-frequency = <24000000>;
clock-div = <4>;
clock-mult = <1>;
};

View File

@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
};
&xo_board_clk {
clock-frequency = <24000000>;
clock-div = <4>;
clock-mult = <1>;
};

View File

@ -44,7 +44,8 @@ sleep_clk: sleep-clk {
};
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
compatible = "fixed-factor-clock";
clocks = <&ref_96mhz_clk>;
#clock-cells = <0>;
};