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arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -120,5 +120,6 @@ &usbphy0 {
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};
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&xo_board_clk {
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clock-frequency = <24000000>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
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};
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&xo_board_clk {
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clock-frequency = <24000000>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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@ -44,7 +44,8 @@ sleep_clk: sleep-clk {
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};
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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compatible = "fixed-factor-clock";
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clocks = <&ref_96mhz_clk>;
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#clock-cells = <0>;
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};
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