From 5c9a79d564da2a741492b2611f3c9bdae4002d65 Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Tue, 28 Apr 2026 12:48:24 +0300 Subject: [PATCH] drm/i915/display: move HSW and BDW clock gating init to display Move the HSW and BDW display clock gating programming into the display code. In this case we need two different helpers, because the common code between these two is split in the middle. Reviewed-by: Jani Nikula Link: https://patch.msgid.link/20260428095104.818360-7-luciano.coelho@intel.com Signed-off-by: Luca Coelho --- .../i915/display/intel_display_clock_gating.c | 44 +++++++++++++++++++ .../i915/display/intel_display_clock_gating.h | 4 ++ .../gpu/drm/i915/display/intel_display_regs.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 3 -- drivers/gpu/drm/i915/intel_clock_gating.c | 34 ++------------ 5 files changed, 55 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c index a8966e6ace38..74bb88d52ba9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c @@ -132,3 +132,47 @@ void intel_display_glk_init_clock_gating(struct intel_display *display) intel_de_read(display, GEN9_CLKGATE_DIS_0) | PWM1_GATING_DIS | PWM2_GATING_DIS); } + +void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display) +{ + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); +} + +void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display) +{ + enum pipe pipe; + + /* WaPsrDPAMaskVBlankInSRD:hsw */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + + for_each_pipe(display, pipe) { + /* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, + BDW_UNMASK_VBL_TO_REGS_IN_SRD); + } +} + +void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display) +{ + /* WaKVMNotificationOnConfigChange:bdw */ + intel_de_rmw(display, CHICKEN_PAR2_1, 0, + KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); +} + +void intel_display_hsw_init_clock_gating(struct intel_display *display) +{ + enum pipe pipe; + + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); + + /* WaPsrDPAMaskVBlankInSRD:hsw */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + + for_each_pipe(display, pipe) { + /* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, + HSW_UNMASK_VBL_TO_REGS_IN_SRD); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h index a7784db9d97a..e0300dc8b041 100644 --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h @@ -13,5 +13,9 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display); void intel_display_cfl_init_clock_gating(struct intel_display *display); void intel_display_bxt_init_clock_gating(struct intel_display *display); void intel_display_glk_init_clock_gating(struct intel_display *display); +void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display); +void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display); +void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display); +void intel_display_hsw_init_clock_gating(struct intel_display *display); #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index dada8dc27ea4..1cb87ba0ebeb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -405,6 +405,9 @@ #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) +#define CHICKEN_PAR2_1 _MMIO(0x42090) +#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) + /* * GEN9 clock gating regs */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5d99b99b0c57..e9d7f1c3a288 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -717,9 +717,6 @@ #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) -#define CHICKEN_PAR2_1 _MMIO(0x42090) -#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) - #define VLV_PMWGICZ _MMIO(0x1300a4) #define HSW_EDRAM_CAP _MMIO(0x120010) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 96fe16753e58..10aa00e003be 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -284,23 +284,12 @@ static void skl_init_clock_gating(struct drm_i915_private *i915) static void bdw_init_clock_gating(struct drm_i915_private *i915) { - struct intel_display *display = i915->display; - enum pipe pipe; - - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); + intel_display_bdw_clock_gating_disable_fbcq(i915->display); /* WaSwitchSolVfFArbitrationPriority:bdw */ intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); - /* WaPsrDPAMaskVBlankInSRD:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); - - for_each_pipe(display, pipe) { - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), - 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); - } + intel_display_bdw_clock_gating_vblank_in_srd(i915->display); /* WaVSRefCountFullforceMissDisable:bdw */ /* WaDSRefCountFullforceMissDisable:bdw */ @@ -316,9 +305,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) /* WaProgramL3SqcReg1Default:bdw */ gen8_set_l3sqc_credits(i915, 30, 2); - /* WaKVMNotificationOnConfigChange:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, - 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); + intel_display_bdw_clock_gating_kvm_notif(i915->display); intel_pch_init_clock_gating(i915->display); @@ -332,20 +319,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) static void hsw_init_clock_gating(struct drm_i915_private *i915) { - struct intel_display *display = i915->display; - enum pipe pipe; - - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); - - /* WaPsrDPAMaskVBlankInSRD:hsw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); - - for_each_pipe(display, pipe) { - /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), - 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); - } + intel_display_hsw_init_clock_gating(i915->display); /* This is required by WaCatErrorRejectionIssue:hsw */ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,