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Merge tag 'riscv-fixes-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into fixes

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riscv fixes for 6.16-rc1

- A fix for the newly introduced getrandom vdso where clang optimizes
  away a register variable which is both an input and an output
  parameter
- A fix for theadvector where we did not save all the vector registers,
  only a few of them

* tag 'riscv-fixes-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux:
  RISC-V: vDSO: Correct inline assembly constraints in the getrandom syscall wrapper
  riscv: vector: Fix context save/restore with xtheadvector
This commit is contained in:
Palmer Dabbelt 2025-06-12 11:59:05 -07:00
commit 5c5ecd1f34
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2 changed files with 7 additions and 7 deletions
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2
arch/riscv/include/asm/vdso/getrandom.h
View File

@ -18,7 +18,7 @@ static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, uns
register unsigned int flags asm("a2") = _flags;
asm volatile ("ecall\n"
: "+r" (ret)
: "=r" (ret)
: "r" (nr), "r" (buffer), "r" (len), "r" (flags)
: "memory");

12
arch/riscv/include/asm/vector.h
View File

@ -205,11 +205,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
THEAD_VSETVLI_T4X0E8M8D1
THEAD_VSB_V_V0T0
"add t0, t0, t4\n\t"
THEAD_VSB_V_V0T0
THEAD_VSB_V_V8T0
"add t0, t0, t4\n\t"
THEAD_VSB_V_V0T0
THEAD_VSB_V_V16T0
"add t0, t0, t4\n\t"
THEAD_VSB_V_V0T0
THEAD_VSB_V_V24T0
: : "r" (datap) : "memory", "t0", "t4");
} else {
asm volatile (
@ -241,11 +241,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
THEAD_VSETVLI_T4X0E8M8D1
THEAD_VLB_V_V0T0
"add t0, t0, t4\n\t"
THEAD_VLB_V_V0T0
THEAD_VLB_V_V8T0
"add t0, t0, t4\n\t"
THEAD_VLB_V_V0T0
THEAD_VLB_V_V16T0
"add t0, t0, t4\n\t"
THEAD_VLB_V_V0T0
THEAD_VLB_V_V24T0
: : "r" (datap) : "memory", "t0", "t4");
} else {
asm volatile (