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SoCFPGA Clock updates for v6.19
- Add the Agilex5 clock driver -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmj6EuAACgkQGZQEC4Gj KPSfNg//RGwNIkblo7AZNaTw1MxFNDYj/HY1P6sUfOrkWuE+gSCUR/dnoZVDcczu eQumUfy/rj0QOKEHdNph1YIyaMHQSbNiadE0w8iNEI3Kg2Qz4SxjPi2eG26VO9NT RYoBnF+qVGzE2kx2kiX3KtCChzcJU5TmA2YU9/02VweN5+6gO+Rq7WzFS/PK78rk iccrn0/+lQX10QQ1xISJdcXEvaESjeiqZzNR8PvaC2wt+tVuUuMi/LdKerR0vJa9 qhjuO+3qR6dLDOMrbxw1z3WR6PowtJJu8OYKKKC1+gKLMrvraqzOF3KZx/XFVCbc +CN0WCP1cJP3ThdJORZP6KVXYXfUir+BeC1Nqc3gTMhCNYz59J6B+3M/sCOJQ9c+ TlANZ4BB/mTLQbP0ug/qMFAfIw2LWJpVYVnptS9U+suYI1Y/iYzQcMXhCV3MeHJf eRDIB9rIk1ERnj7eV3jexByZBM609Y5v8F5/98Ud436xAoCiceIthBUunvxge7RC hUPJ83G9t/ZBIcyeCzS5ffobNc7UGcotue1+3N8g/DuhJmVhCKSm/YMiNxeZXMAK piLlDYtgVR1+hnIdqTjvRW7VmvPNRYK7P8x4OE0itaGkzXyn9i7ARdtKfTY+Uwn5 hLFO/gd1CLOYX6nWGf5ynANtVdYF/yS1I+hpuOteg2hrMJHnuQY= =TLCO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmkSiX8UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWHUA//Xslf4UOjTlvy5a2VipmeN2ec7jfi JFbUb/b8gDUTgv4iRhydZNbmc0kMjdlSHFVQkyaP5oT5SxXeJZ1BhiPpSM/yJEpj rdHxw0tDu8VK5vxmk8SYIawGIucn4DWLFLhK+9OZ0XQtiPWCFEjfCtUJmDhPm7D/ 7+nmkZUL6SumaOLLzDp/Fj5Cht690GuSfHckibgXzwr99paZ8j6eRGgtHEo+1eXB SE1hrLmzOyokzGIzImAlaCITE1K8BQO23oxxMNYbTvBZkwpfrfHYw4BI315z9JaB vwIEfJp4ShskC+S3ac4eDBSQngKeyvHfu0QNISeWQFz4hv/uHBt48l01a7G5PxcG dJ/VMpVIBKRswRNZOzifxgOhVnaRGoR4cPeqxZe91w+Ex5sow3oYxhBPVh04+a2p QxJG2cJhPMVyenWCgcpIsJzSlvI4CDwFwbtC8GHCfn7Agyw8X4X5efpvTWTKK84e VAD/O/s59beBKGwh7IJtWSg40UzF58fN0IZvfzpexRtzEcut1dSr0msoT/iPHx4O nCYHCjbyyBeie36E45zBDH+XwJX+S1wCuKxl35CnIijQrvhtznVjA3VWz34GE0Zg QbVd5QiM2NK0s1dOQiRJYSHonkzgUe9KDqXVo1Nl9PrZiYX/xNBt15t/OmwOLynl 88YqDnoIG53IM90= =hTZe -----END PGP SIGNATURE----- Merge tag 'socfpga_clk_for_v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga Pull SoCFPGA clk driver updates from Dinh Nguyen: - Add the Agilex5 clock driver * tag 'socfpga_clk_for_v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: clk: socfpga: agilex5: add clock driver for Agilex5
This commit is contained in:
Stephen Boyd
commit
5c534939dd
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@ -13,7 +13,7 @@ config CLK_INTEL_SOCFPGA32
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default ARM && ARCH_INTEL_SOCFPGA
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config CLK_INTEL_SOCFPGA64
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bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
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bool "Intel Stratix / Agilex / N5X / Agilex5 clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
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default ARM64 && ARCH_INTEL_SOCFPGA
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endif # CLK_INTEL_SOCFPGA
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@ -3,4 +3,4 @@ obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
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clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
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obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
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clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
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clk-agilex.o
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clk-agilex.o clk-agilex5.o
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561
drivers/clk/socfpga/clk-agilex5.c
Normal file
561
drivers/clk/socfpga/clk-agilex5.c
Normal file
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@ -0,0 +1,561 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022-2024, Intel Corporation
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* Copyright (C) 2025, Altera Corporation
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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/* External parent clocks come from DT via fw_name */
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static const char * const boot_pll_parents[] = {
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"osc1",
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"cb-intosc-hs-div2-clk",
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};
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static const char * const main_pll_parents[] = {
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const periph_pll_parents[] = {
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"osc1",
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"cb-intosc-hs-div2-clk",
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};
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/* Core free muxes */
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static const char * const core0_free_mux[] = {
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"main_pll_c1",
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"peri_pll_c0",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const core1_free_mux[] = {
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"main_pll_c1",
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"peri_pll_c0",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const core2_free_mux[] = {
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"main_pll_c0",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const core3_free_mux[] = {
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"main_pll_c0",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const dsu_free_mux[] = {
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"main_pll_c2",
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"peri_pll_c0",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const noc_free_mux[] = {
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"main_pll_c3",
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"peri_pll_c1",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const emac_ptp_free_mux[] = {
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"main_pll_c3",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const emaca_free_mux[] = {
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"main_pll_c2",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const emacb_free_mux[] = {
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"main_pll_c3",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const gpio_db_free_mux[] = {
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"main_pll_c3",
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"peri_pll_c1",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const psi_ref_free_mux[] = {
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"main_pll_c1",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const usb31_free_mux[] = {
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"main_pll_c3",
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"peri_pll_c2",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const s2f_user0_free_mux[] = {
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"main_pll_c1",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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static const char * const s2f_user1_free_mux[] = {
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"main_pll_c1",
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"peri_pll_c3",
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"osc1",
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"cb-intosc-hs-div2-clk",
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"f2s-free-clk",
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};
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/* Secondary muxes between free_clk and boot_clk */
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static const char * const core0_mux[] = {
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"core0_free_clk",
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"boot_clk",
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};
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static const char * const core1_mux[] = {
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"core1_free_clk",
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"boot_clk",
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};
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static const char * const core2_mux[] = {
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"core2_free_clk",
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"boot_clk",
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};
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static const char * const core3_mux[] = {
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"core3_free_clk",
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"boot_clk",
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};
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static const char * const dsu_mux[] = {
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"dsu_free_clk",
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"boot_clk",
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};
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static const char * const noc_mux[] = {
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"noc_free_clk",
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"boot_clk",
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};
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static const char * const emac_mux[] = {
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"emaca_free_clk",
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"emacb_free_clk",
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"boot_clk",
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};
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static const char * const s2f_user0_mux[] = {
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"s2f_user0_free_clk",
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"boot_clk",
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};
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static const char * const s2f_user1_mux[] = {
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"s2f_user1_free_clk",
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"boot_clk",
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};
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static const char * const psi_mux[] = {
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"psi_ref_free_clk",
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"boot_clk",
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};
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static const char * const gpio_db_mux[] = {
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"gpio_db_free_clk",
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"boot_clk",
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};
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static const char * const emac_ptp_mux[] = {
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"emac_ptp_free_clk",
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"boot_clk",
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};
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static const char * const usb31_mux[] = {
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"usb31_free_clk",
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"boot_clk",
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};
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static const struct agilex5_pll_clock agilex5_pll_clks[] = {
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{
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.id = AGILEX5_BOOT_CLK,
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.name = "boot_clk",
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.parent_names = boot_pll_parents,
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.num_parents = ARRAY_SIZE(boot_pll_parents),
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.flags = 0,
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.offset = 0x0,
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},
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{
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.id = AGILEX5_MAIN_PLL_CLK,
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.name = "main_pll",
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.parent_names = main_pll_parents,
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.num_parents = ARRAY_SIZE(main_pll_parents),
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.flags = 0,
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.offset = 0x48,
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},
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{
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.id = AGILEX5_PERIPH_PLL_CLK,
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.name = "periph_pll",
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.parent_names = periph_pll_parents,
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.num_parents = ARRAY_SIZE(periph_pll_parents),
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.flags = 0,
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.offset = 0x9C,
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},
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};
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/* Main PLL C0, C1, C2, C3 and Peri PLL C0, C1, C2, C3. With ping-pong counter. */
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static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
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{ AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0,
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0x5C },
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{ AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0,
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0x60 },
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{ AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0,
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0x64 },
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{ AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0,
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0x68 },
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{ AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
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0xB0 },
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{ AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
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0xB4 },
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{ AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
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0xB8 },
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{ AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
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0xBC },
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};
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/* Non-SW clock-gated enabled clocks */
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static const struct agilex5_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
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{ AGILEX5_CORE0_FREE_CLK, "core0_free_clk", core0_free_mux,
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ARRAY_SIZE(core0_free_mux), 0, 0x0100, 0, 0, 0},
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{ AGILEX5_CORE1_FREE_CLK, "core1_free_clk", core1_free_mux,
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ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0},
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{ AGILEX5_CORE2_FREE_CLK, "core2_free_clk", core2_free_mux,
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ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0},
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{ AGILEX5_CORE3_FREE_CLK, "core3_free_clk", core3_free_mux,
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ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0},
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{ AGILEX5_DSU_FREE_CLK, "dsu_free_clk", dsu_free_mux,
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ARRAY_SIZE(dsu_free_mux), 0, 0xfc, 0, 0, 0},
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{ AGILEX5_NOC_FREE_CLK, "noc_free_clk", noc_free_mux,
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ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
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{ AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", emaca_free_mux,
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ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 },
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{ AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", emacb_free_mux,
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ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 },
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{ AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", emac_ptp_free_mux,
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ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2 },
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{ AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", gpio_db_free_mux,
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ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 },
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{ AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", s2f_user0_free_mux,
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ARRAY_SIZE(s2f_user0_free_mux), 0, 0xE8, 0, 0x30, 2 },
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{ AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", s2f_user1_free_mux,
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ARRAY_SIZE(s2f_user1_free_mux), 0, 0xEC, 0, 0x88, 5 },
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{ AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", psi_ref_free_mux,
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ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 },
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{ AGILEX5_USB31_FREE_CLK, "usb31_free_clk", usb31_free_mux,
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ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7},
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};
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static const char * const cs_pdbg_parents[] = { "cs_at_clk" };
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static const char * const usb31_bus_clk_early_parents[] = { "l4_main_clk" };
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static const char * const l4_mp_clk_parent[] = { "l4_mp_clk" };
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static const char * const l4_sp_clk_parent[] = { "l4_sp_clk" };
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static const char * const dfi_clk_parent[] = { "dfi_clk" };
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/* SW Clock gate enabled clocks */
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static const struct agilex5_gate_clock agilex5_gate_clks[] = {
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{ AGILEX5_CORE0_CLK, "core0_clk", core0_mux,
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ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 },
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{ AGILEX5_CORE1_CLK, "core1_clk", core1_mux,
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ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 },
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{ AGILEX5_CORE2_CLK, "core2_clk", core2_mux,
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ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 },
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{ AGILEX5_CORE3_CLK, "core3_clk", core3_mux,
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ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 },
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{ AGILEX5_MPU_CLK, "dsu_clk", dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0, 0,
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0, 0, 0, 0x34, 4, 0 },
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{ AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", dsu_mux,
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ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 },
|
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{ AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", dsu_mux,
|
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ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 },
|
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{ AGILEX5_L4_MAIN_CLK, "l4_main_clk", noc_mux, ARRAY_SIZE(noc_mux),
|
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CLK_IS_CRITICAL, 0x24, 1, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_L4_MP_CLK, "l4_mp_clk", noc_mux, ARRAY_SIZE(noc_mux), 0,
|
||||
0x24, 2, 0x44, 4, 2, 0x30, 1, 0 },
|
||||
{ AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", noc_mux,
|
||||
ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 },
|
||||
{ AGILEX5_L4_SP_CLK, "l4_sp_clk", noc_mux, ARRAY_SIZE(noc_mux),
|
||||
CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 },
|
||||
|
||||
/* Core sight clocks*/
|
||||
{ AGILEX5_CS_AT_CLK, "cs_at_clk", noc_mux, ARRAY_SIZE(noc_mux), 0,
|
||||
0x24, 4, 0x44, 24, 2, 0x30, 1, 0 },
|
||||
{ AGILEX5_CS_TRACE_CLK, "cs_trace_clk", noc_mux,
|
||||
ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 },
|
||||
{ AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", cs_pdbg_parents, 1, 0, 0x24, 4,
|
||||
0x44, 28, 1, 0, 0, 0 },
|
||||
|
||||
/* Main Peripheral PLL1 Begin */
|
||||
{ AGILEX5_EMAC0_CLK, "emac0_clk", emac_mux, ARRAY_SIZE(emac_mux),
|
||||
0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 },
|
||||
{ AGILEX5_EMAC1_CLK, "emac1_clk", emac_mux, ARRAY_SIZE(emac_mux),
|
||||
0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 },
|
||||
{ AGILEX5_EMAC2_CLK, "emac2_clk", emac_mux, ARRAY_SIZE(emac_mux),
|
||||
0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 },
|
||||
{ AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", emac_ptp_mux,
|
||||
ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 },
|
||||
{ AGILEX5_GPIO_DB_CLK, "gpio_db_clk", gpio_db_mux,
|
||||
ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 1 },
|
||||
/* Main Peripheral PLL1 End */
|
||||
|
||||
/* Peripheral clocks */
|
||||
{ AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", s2f_user0_mux,
|
||||
ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 },
|
||||
{ AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", s2f_user1_mux,
|
||||
ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 },
|
||||
{ AGILEX5_PSI_REF_CLK, "psi_ref_clk", psi_mux,
|
||||
ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 },
|
||||
{ AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", usb31_mux,
|
||||
ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 },
|
||||
{ AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", usb31_bus_clk_early_parents,
|
||||
1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", l4_mp_clk_parent, 1, 0, 0x7C,
|
||||
8, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPIM_0_CLK, "spim_0_clk", l4_mp_clk_parent, 1, 0, 0x7C, 9,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPIM_1_CLK, "spim_1_clk", l4_mp_clk_parent, 1, 0, 0x7C, 11,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPIS_0_CLK, "spis_0_clk", l4_sp_clk_parent, 1, 0, 0x7C, 12,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPIS_1_CLK, "spis_1_clk", l4_sp_clk_parent, 1, 0, 0x7C, 13,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_DMA_CORE_CLK, "dma_core_clk", l4_mp_clk_parent, 1, 0, 0x7C,
|
||||
14, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_DMA_HS_CLK, "dma_hs_clk", l4_mp_clk_parent, 1, 0, 0x7C, 14,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", l4_mp_clk_parent, 1, 0,
|
||||
0x7C, 18, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", l4_mp_clk_parent, 1, 0,
|
||||
0x7C, 19, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I2C_0_PCLK, "i2c_0_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 15,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I2C_1_PCLK, "i2c_1_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 16,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", l4_sp_clk_parent, 1, 0,
|
||||
0x7C, 17, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", l4_sp_clk_parent, 1, 0,
|
||||
0x7C, 22, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", l4_sp_clk_parent, 1, 0,
|
||||
0x7C, 27, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_UART_0_PCLK, "uart_0_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 20,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_UART_1_PCLK, "uart_1_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 21,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", l4_sp_clk_parent, 1, 0,
|
||||
0x7C, 23, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", l4_sp_clk_parent, 1, 0,
|
||||
0x7C, 24, 0, 0, 0, 0, 0, 0 },
|
||||
|
||||
/*NAND, SD/MMC and SoftPHY overall clocking*/
|
||||
{ AGILEX5_DFI_CLK, "dfi_clk", l4_mp_clk_parent, 1, 0, 0, 0, 0x44, 16,
|
||||
2, 0, 0, 0 },
|
||||
{ AGILEX5_NAND_NF_CLK, "nand_nf_clk", dfi_clk_parent, 1, 0, 0x7C, 10,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_NAND_BCH_CLK, "nand_bch_clk", l4_mp_clk_parent, 1, 0, 0x7C,
|
||||
10, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", l4_mp_clk_parent,
|
||||
1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SDMCLK, "sdmclk", dfi_clk_parent, 1, 0, 0x7C, 5, 0, 0, 0,
|
||||
0, 0, 0 },
|
||||
{ AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", l4_mp_clk_parent, 1, 0,
|
||||
0x7C, 26, 0, 0, 0, 0, 0, 0 },
|
||||
{ AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", l4_mp_clk_parent, 1, 0,
|
||||
0x7C, 26, 0x44, 16, 2, 0, 0, 0 },
|
||||
{ AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", dfi_clk_parent, 1, 0,
|
||||
0x7C, 26, 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static int
|
||||
agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
hw_clk = s10_register_periph(&clks[i], base);
|
||||
if (IS_ERR(hw_clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.hws[clks[i].id] = hw_clk;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
agilex5_clk_register_cnt_perip(const struct agilex5_perip_cnt_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
hw_clk = agilex5_register_cnt_periph(&clks[i], base);
|
||||
if (IS_ERR(hw_clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.hws[clks[i].id] = hw_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int agilex5_clk_register_gate(const struct agilex5_gate_clock *clks,
|
||||
int nums,
|
||||
struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
hw_clk = agilex5_register_gate(&clks[i], base);
|
||||
if (IS_ERR(hw_clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.hws[clks[i].id] = hw_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int agilex5_clk_register_pll(const struct agilex5_pll_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
hw_clk = agilex5_register_pll(&clks[i], base);
|
||||
if (IS_ERR(hw_clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.hws[clks[i].id] = hw_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int agilex5_clkmgr_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct stratix10_clock_data *clk_data;
|
||||
void __iomem *base;
|
||||
int i, num_clks;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
num_clks = AGILEX5_NUM_CLKS;
|
||||
|
||||
clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
|
||||
num_clks), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data->base = base;
|
||||
clk_data->clk_data.num = num_clks;
|
||||
|
||||
for (i = 0; i < num_clks; i++)
|
||||
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks),
|
||||
clk_data);
|
||||
|
||||
/* mainPLL C0, C1, C2, C3 and periph PLL C0, C1, C2, C3*/
|
||||
agilex5_clk_register_c_perip(agilex5_main_perip_c_clks,
|
||||
ARRAY_SIZE(agilex5_main_perip_c_clks),
|
||||
clk_data);
|
||||
|
||||
agilex5_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
|
||||
ARRAY_SIZE(agilex5_main_perip_cnt_clks),
|
||||
clk_data);
|
||||
|
||||
agilex5_clk_register_gate(agilex5_gate_clks,
|
||||
ARRAY_SIZE(agilex5_gate_clks), clk_data);
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int agilex5_clkmgr_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*probe_func)(struct platform_device *init_func);
|
||||
|
||||
probe_func = of_device_get_match_data(&pdev->dev);
|
||||
if (!probe_func)
|
||||
return -ENODEV;
|
||||
return probe_func(pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id agilex5_clkmgr_match_table[] = {
|
||||
{ .compatible = "intel,agilex5-clkmgr", .data = agilex5_clkmgr_init },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver agilex5_clkmgr_driver = {
|
||||
.probe = agilex5_clkmgr_probe,
|
||||
.driver = {
|
||||
.name = "agilex5-clkmgr",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = agilex5_clkmgr_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init agilex5_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&agilex5_clkmgr_driver);
|
||||
}
|
||||
core_initcall(agilex5_clk_init);
|
||||
|
|
@ -239,3 +239,56 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
|
|||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
||||
struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void __iomem *regbase)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
struct socfpga_gate_clk *socfpga_clk;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
|
||||
if (!socfpga_clk)
|
||||
return NULL;
|
||||
|
||||
socfpga_clk->hw.reg = regbase + clks->gate_reg;
|
||||
socfpga_clk->hw.bit_idx = clks->gate_idx;
|
||||
|
||||
gateclk_ops.enable = clk_gate_ops.enable;
|
||||
gateclk_ops.disable = clk_gate_ops.disable;
|
||||
|
||||
socfpga_clk->fixed_div = clks->fixed_div;
|
||||
|
||||
if (clks->div_reg)
|
||||
socfpga_clk->div_reg = regbase + clks->div_reg;
|
||||
else
|
||||
socfpga_clk->div_reg = NULL;
|
||||
|
||||
socfpga_clk->width = clks->div_width;
|
||||
socfpga_clk->shift = clks->div_offset;
|
||||
|
||||
if (clks->bypass_reg)
|
||||
socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
|
||||
else
|
||||
socfpga_clk->bypass_reg = NULL;
|
||||
socfpga_clk->bypass_shift = clks->bypass_shift;
|
||||
|
||||
if (streq(clks->name, "cs_pdbg_clk"))
|
||||
init.ops = &dbgclk_ops;
|
||||
else
|
||||
init.ops = &agilex_gateclk_ops;
|
||||
|
||||
init.name = clks->name;
|
||||
init.flags = clks->flags;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = clks->parent_names;
|
||||
socfpga_clk->hw.hw.init = &init;
|
||||
hw_clk = &socfpga_clk->hw.hw;
|
||||
|
||||
ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
|
||||
if (ret) {
|
||||
kfree(socfpga_clk);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -214,3 +214,44 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
|
|||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
||||
struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock *clks,
|
||||
void __iomem *regbase)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
struct socfpga_periph_clk *periph_clk;
|
||||
struct clk_init_data init;
|
||||
const char *name = clks->name;
|
||||
int ret;
|
||||
|
||||
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!periph_clk))
|
||||
return NULL;
|
||||
|
||||
if (clks->offset)
|
||||
periph_clk->hw.reg = regbase + clks->offset;
|
||||
else
|
||||
periph_clk->hw.reg = NULL;
|
||||
|
||||
if (clks->bypass_reg)
|
||||
periph_clk->bypass_reg = regbase + clks->bypass_reg;
|
||||
else
|
||||
periph_clk->bypass_reg = NULL;
|
||||
periph_clk->bypass_shift = clks->bypass_shift;
|
||||
periph_clk->fixed_div = clks->fixed_divider;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &peri_cnt_clk_ops;
|
||||
init.flags = clks->flags;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = clks->parent_names;
|
||||
periph_clk->hw.hw.init = &init;
|
||||
hw_clk = &periph_clk->hw.hw;
|
||||
|
||||
ret = clk_hw_register(NULL, hw_clk);
|
||||
if (ret) {
|
||||
kfree(periph_clk);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -304,3 +304,39 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
|
|||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
||||
struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
|
||||
void __iomem *reg)
|
||||
{
|
||||
struct clk_hw *hw_clk;
|
||||
struct socfpga_pll *pll_clk;
|
||||
struct clk_init_data init;
|
||||
const char *name = clks->name;
|
||||
int ret;
|
||||
|
||||
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!pll_clk))
|
||||
return NULL;
|
||||
|
||||
pll_clk->hw.reg = reg + clks->offset;
|
||||
|
||||
if (streq(name, SOCFPGA_BOOT_CLK))
|
||||
init.ops = &clk_boot_ops;
|
||||
else
|
||||
init.ops = &agilex_clk_pll_ops;
|
||||
|
||||
init.name = name;
|
||||
init.flags = clks->flags;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = clks->parent_names;
|
||||
pll_clk->hw.hw.init = &init;
|
||||
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
|
||||
hw_clk = &pll_clk->hw.hw;
|
||||
|
||||
ret = clk_hw_register(NULL, hw_clk);
|
||||
if (ret) {
|
||||
kfree(pll_clk);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return hw_clk;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -73,12 +73,55 @@ struct stratix10_gate_clock {
|
|||
u8 fixed_div;
|
||||
};
|
||||
|
||||
struct agilex5_pll_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char * const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
};
|
||||
|
||||
struct agilex5_perip_cnt_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char * const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 fixed_divider;
|
||||
unsigned long bypass_reg;
|
||||
unsigned long bypass_shift;
|
||||
};
|
||||
|
||||
struct agilex5_gate_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char * const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long gate_reg;
|
||||
u8 gate_idx;
|
||||
unsigned long div_reg;
|
||||
u8 div_offset;
|
||||
u8 div_width;
|
||||
unsigned long bypass_reg;
|
||||
u8 bypass_shift;
|
||||
u8 fixed_div;
|
||||
};
|
||||
|
||||
struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
|
||||
void __iomem *reg);
|
||||
struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
|
||||
void __iomem *reg);
|
||||
struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
|
||||
void __iomem *reg);
|
||||
struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
|
||||
void __iomem *reg);
|
||||
struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock *clks,
|
||||
void __iomem *regbase);
|
||||
struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks,
|
||||
void __iomem *regbase);
|
||||
struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
|
||||
void __iomem *reg);
|
||||
struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user