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ARM: tegra: Changes for v5.17-rc1

Browse Source 
A large part of this is cleanups to existing device trees in order to
 improve validation of the device trees using the dt-schema tooling.
 
 This also contains a set of new device trees for various boards that
 have been contributed by community members as well as fixes to existing
 devices.
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Merge tag 'tegra-for-5.17-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

ARM: tegra: Changes for v5.17-rc1

A large part of this is cleanups to existing device trees in order to
improve validation of the device trees using the dt-schema tooling.

This also contains a set of new device trees for various boards that
have been contributed by community members as well as fixes to existing
devices.

* tag 'tegra-for-5.17-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (55 commits)
  ARM: tegra: Add host1x hotflush reset on Tegra124
  ARM: tegra: Add memory client hotflush resets on Tegra114
  ARM: tegra: Add back gpio-ranges properties
  ARM: tegra: paz00: Enable S/PDIF and HDMI audio
  ARM: tegra: acer-a500: Enable S/PDIF and HDMI audio
  ARM: tegra: Add HDMI audio graph to Tegra20 device-tree
  ARM: tegra: Add S/PDIF node to Tegra20 device-tree
  ARM: tegra20/30: Disable unused host1x hardware
  ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x
  ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x
  ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees
  ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees
  ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table
  ARM: tegra: Enable video decoder on Tegra114
  ARM: tegra: nexus7: Use common LVDS display device-tree
  ARM: tegra: Add CPU thermal zones to Nyan device-tree
  ARM: tegra: Enable CPU DFLL on Nyan
  ARM: tegra: Enable HDMI CEC on Nyan
  ARM: tegra: Add usb-role-switch property to USB OTG ports
  ARM: tegra: Add device-tree for 1080p version of Nyan Big
  ...

Link: https://lore.kernel.org/r/20211217162253.1801077-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-20 17:14:05 +01:00
commit 5c4a5b36e4
65 changed files with 19833 additions and 6577 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/Makefile
View File

@ -1317,6 +1317,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-tf101.dtb \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
@ -1333,12 +1334,18 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-asus-tf201.dtb \
tegra30-asus-tf300t.dtb \
tegra30-asus-tf300tg.dtb \
tegra30-asus-tf700t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb \
tegra30-ouya.dtb
tegra30-ouya.dtb \
tegra30-pegatron-chagall.dtb
dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb
@ -1347,6 +1354,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-apalis-v1.2-eval.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-nyan-big-fhd.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U8500) += \

807
arch/arm/boot/dts/tegra114-asus-tf701t.dts Normal file
View File

@ -0,0 +1,807 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include "tegra114.dtsi"
/ {
model = "Asus Transformer Pad TF701T";
compatible = "asus,tf701t", "nvidia,tegra114";
chassis-type = "convertible";
aliases {
mmc0 = "/mmc@78000600"; /* eMMC */
mmc1 = "/mmc@78000400"; /* uSD slot */
mmc2 = "/mmc@78000000"; /* WiFi */
rtc0 = &palmas;
rtc1 = "/rtc@7000e000";
serial0 = &uartd; /* Console */
serial1 = &uartc; /* Bluetooth */
serial2 = &uartb; /* GPS */
};
memory@80000000 {
reg = <0x80000000 0x80000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma@80000000 {
compatible = "shared-dma-pool";
alloc-ranges = <0x80000000 0x30000000>;
size = <0x10000000>;
linux,cma-default;
reusable;
};
trustzone@bfe00000 {
reg = <0xbfe00000 0x200000>;
no-map;
};
};
host1x@50000000 {
dsi@54300000 {
status = "okay";
avdd-dsi-csi-supply = <&tps65913_ldo2>;
nvidia,ganged-mode = <&dsib>;
panel_primary: panel@0 {
compatible = "sharp,lq101r1sx01";
reg = <0>;
link2 = <&panel_secondary>;
power-supply = <&vdd_lcd>;
backlight = <&backlight>;
};
};
dsi@54400000 {
status = "okay";
avdd-dsi-csi-supply = <&tps65913_ldo2>;
panel_secondary: panel@0 {
compatible = "sharp,lq101r1sx01";
reg = <0>;
};
};
};
pinmux@70000868 {
asus_pad_ec_default: asus-pad-ec-default {
ec-interrupt {
nvidia,pins = "kb_col5_pq5";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ec-request {
nvidia,pins = "kb_col2_pq2";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
backlight_default: backlight-default {
backlight-enable {
nvidia,pins = "gmi_ad10_ph2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
codec_default: codec-default {
ldo1-en {
nvidia,pins = "sdmmc1_wp_n_pv3";
nvidia,function = "sdmmc1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
interrupt {
nvidia,pins = "gpio_w2_aud_pw2",
"gpio_w3_aud_pw3";
nvidia,function = "spi6";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
gpio_keys_default: gpio-keys-default {
power {
nvidia,pins = "kb_col0_pq0";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
volume {
nvidia,pins = "kb_row1_pr1",
"kb_row2_pr2";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
gpio_hall_sensor_default: gpio-hall-sensor-default {
ulpi_data4_po5 {
nvidia,pins = "ulpi_data4_po5";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
hp_det_default: hp-det-default {
gmi_iordy_pi5 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
imu_default: imu-default {
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3";
nvidia,function = "rsvd3";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
pwm_default: pwm-default {
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
/* XXX make this something more sensible */
pwm_sleep: pwm-sleep {
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
sdmmc3_default: sdmmc3-default {
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"kb_col4_pq4",
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5",
"sdmmc3_cd_n_pv2";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
drive_sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,pull-down-strength = <22>;
nvidia,pull-up-strength = <36>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
};
sdmmc3_vdd_default: sdmmc3-vdd-default {
gmi_clk_pk1 {
nvidia,pins = "gmi_clk_pk1";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
vdd_lcd_default: vdd-lcd-default {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
serial@70006040 {
/* GPS */
};
serial@70006200 {
/* Bluetooth */
};
serial@70006300 {
status = "okay";
};
pwm@7000a000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pwm_default>;
pinctrl-1 = <&pwm_sleep>;
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
magnetometer@c {
compatible = "asahi-kasei,ak09911";
reg = <0xc>;
vdd-supply = <&vdd_3v3_sys>;
};
rt5639: audio-codec@1c {
compatible = "realtek,rt5639";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&codec_default>;
};
motion-tracker@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>;
mount-matrix = "0", "-1", "0",
"1", "0", "0",
"0", "0", "1";
pinctrl-names = "default";
pinctrl-0 = <&imu_default>;
};
temp_sensor: temperature-sensor@4c {
compatible = "onnn,nct1008";
reg = <0x4c>;
vcc-supply = <&vdd_3v3_sys>;
#thermal-sensor-cells = <1>;
};
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
power-sensor@44 {
compatible = "ti,ina230";
reg = <0x44>;
};
};
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
light-sensor@1c {
compatible = "dynaimage,al3320a";
reg = <0x1c>;
vdd-supply = <&vdd_3v3_sys>;
};
};
i2c@7000c700 {
/* HDMI DDC */
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
palmas: pmic@58 {
compatible = "ti,tps65913", "ti,palmas";
reg = <0x58>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
palmas_gpio: gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
pmic {
compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
ldo1-in-supply = <&tps65913_smps7>;
ldo2-in-supply = <&tps65913_smps7>;
ldo4-in-supply = <&tps65913_smps8>;
ldo5-in-supply = <&tps65913_smps9>;
ldo6-in-supply = <&tps65913_smps9>;
ldo7-in-supply = <&tps65913_smps9>;
ldo9-in-supply = <&tps65913_smps9>;
regulators {
tps65913_smps123: smps123 {
regulator-name = "vdd-cpu";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
ti,roof-floor = <1>;
ti,mode-sleep = <3>;
};
tps65913_smps45: smps45 {
regulator-name = "vdd-core";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
ti,roof-floor = <3>;
};
smps6 {
regulator-name = "va-lcd-hv";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
tps65913_smps7: smps7 {
regulator-name = "vdd-ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
tps65913_smps8: smps8 {
regulator-name = "vdd-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
tps65913_smps9: smps9 {
regulator-name = "vdd-sd";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
tps65913_smps10_out1: smps10_out1 {
regulator-name = "vd-smps10-out1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
tps65913_smps10_out2: smps10_out2 {
regulator-name = "vd-smps10-out2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
tps65913_ldo1: ldo1 {
regulator-name = "vdd-hdmi-pll";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
ti,roof-floor = <3>;
};
tps65913_ldo2: ldo2 {
regulator-name = "vdd-2v8-dsi-csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
ldo3 {
regulator-name = "vpp-fuse";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo4 {
regulator-name = "vdd-1v2-cam";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo5 {
regulator-name = "vdd-cam";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo6 {
regulator-name = "vdd-dev";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
};
ldo7 {
regulator-name = "vdd-2v8-cam";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
tps65913_ldo8: ldo8 {
regulator-name = "vdd-rtc";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
regulator-always-on;
regulator-boot-on;
ti,enable-ldo8-tracking;
};
tps65913_ldo9: ldo9 {
regulator-name = "vdd-sdmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
};
tps65913_ldoln: ldoln {
regulator-name = "vdd-hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldousb {
regulator-name = "vdd-usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&palmas>;
interrupts = <8 0>;
};
pinmux {
compatible = "ti,tps65913-pinctrl";
ti,palmas-enable-dvfs1;
pinctrl-names = "default";
pinctrl-0 = <&palmas_default>;
palmas_default: pinmux {
pin_powergood {
pins = "powergood";
function = "powergood";
};
pin_vac {
pins = "vac";
function = "vac";
};
pin_gpio0 {
pins = "gpio0";
function = "gpio";
};
pin_gpio1 {
pins = "gpio1";
function = "gpio";
};
pin_gpio2 {
pins = "gpio2";
function = "gpio";
};
pin_gpio3 {
pins = "gpio3";
function = "gpio";
};
pin_gpio4 {
pins = "gpio4";
function = "gpio";
};
pin_gpio5 {
pins = "gpio5";
function = "gpio";
};
pin_gpio6 {
pins = "gpio6";
function = "gpio";
};
pin_gpio7 {
pins = "gpio7";
function = "gpio";
};
};
};
};
};
ahub@70080000 {
i2s@70080300 {
status = "okay";
};
};
mmc@78000000 {
/* WiFi */
};
/* MicroSD card */
mmc@78000400 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
nvidia,default-tap = <0x3>;
nvidia,default-trim = <0x3>;
vmmc-supply = <&vdd_usd>;
vqmmc-supply = <&tps65913_ldo9>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc3_default>;
};
mmc@78000600 {
/* eMMC */
};
usb@7d000000 {
compatible = "nvidia,tegra114-udc";
status = "okay";
dr_mode = "peripheral";
/* Peripheral USB via ASUS connector */
};
usb-phy@7d000000 {
status = "okay";
};
usb@7d008000 {
status = "okay";
/* Host USB via dock */
};
usb-phy@7d008000 {
status = "okay";
vbus-supply = <&vdd_5v0_sys>;
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_5v0_sys>;
pwms = <&pwm 1 1000000>;
brightness-levels = <1 255>;
num-interpolated-steps = <254>;
default-brightness-level = <224>;
pinctrl-names = "default";
pinctrl-0 = <&backlight_default>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
firmware {
trusted-foundations {
compatible = "tlm,trusted-foundations";
tlm,version-major = <2>;
tlm,version-minor = <8>;
};
};
gpio-keys {
compatible = "gpio-keys";
label = "GPIO Buttons";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <10>;
wakeup-source;
};
volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
label = "GPIO Hall Effect Sensor";
pinctrl-names = "default";
pinctrl-0 = <&gpio_hall_sensor_default>;
hall-sensor {
label = "Hall Effect Sensor";
gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
wakeup-source;
};
};
sound {
compatible = "asus,tegra-audio-rt5639-tf701t",
"nvidia,tegra-audio-rt5640";
nvidia,model = "Asus Transformer Pad TF701T RT5639";
nvidia,audio-routing =
"Headphones", "HPOR",
"Headphones", "HPOL",
"Speakers", "SPORP",
"Speakers", "SPORN",
"Speakers", "SPOLP",
"Speakers", "SPOLN",
"Mic Jack", "MICBIAS1",
"IN2P", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s0>;
nvidia,audio-codec = <&rt5639>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
<&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA114_CLK_EXTERN1>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det_default>;
};
vdd_5v0_sys: regulator-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3_sys: regulator-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_lcd: regulator-vdd-lcd {
compatible = "regulator-fixed";
regulator-name = "vdd_lcd_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&tps65913_smps8>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
regulator-boot-on;
pinctrl-names = "default";
pinctrl-0 = <&vdd_lcd_default>;
};
vdd_usd: regulator-vdd-usd {
compatible = "regulator-fixed";
regulator-name = "vdd_sd_slot";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
vin-supply = <&tps65913_smps9>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc3_vdd_default>;
};
};

21
arch/arm/boot/dts/tegra114-dalmore.dts
View File

@ -894,7 +894,7 @@ ldo2 {
};
palmas: tps65913@58 {
compatible = "ti,palmas";
compatible = "ti,tps65913", "ti,palmas";
reg = <0x58>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
@ -1084,7 +1084,8 @@ pin_gpio6 {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@0 {
flash@0 {
compatible = "winbond,w25q32dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
@ -1151,7 +1152,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1186,7 +1187,7 @@ volume_up {
};
};
vdd_ac_bat_reg: regulator@0 {
vdd_ac_bat_reg: regulator-acbat {
compatible = "regulator-fixed";
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
@ -1194,7 +1195,7 @@ vdd_ac_bat_reg: regulator@0 {
regulator-always-on;
};
dvdd_ts_reg: regulator@1 {
dvdd_ts_reg: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "dvdd_ts";
regulator-min-microvolt = <1800000>;
@ -1203,7 +1204,7 @@ dvdd_ts_reg: regulator@1 {
gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@3 {
usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@ -1214,7 +1215,7 @@ usb1_vbus_reg: regulator@3 {
vin-supply = <&tps65090_dcdc1_reg>;
};
usb3_vbus_reg: regulator@4 {
usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
@ -1225,7 +1226,7 @@ usb3_vbus_reg: regulator@4 {
vin-supply = <&tps65090_dcdc1_reg>;
};
vdd_hdmi_reg: regulator@5 {
vdd_hdmi_reg: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "vdd_hdmi_5v0";
regulator-min-microvolt = <5000000>;
@ -1233,7 +1234,7 @@ vdd_hdmi_reg: regulator@5 {
vin-supply = <&tps65090_dcdc1_reg>;
};
vdd_cam_1v8_reg: regulator@6 {
vdd_cam_1v8_reg: regulator-cam {
compatible = "regulator-fixed";
regulator-name = "vdd_cam_1v8_reg";
regulator-min-microvolt = <1800000>;
@ -1242,7 +1243,7 @@ vdd_cam_1v8_reg: regulator@6 {
gpio = <&palmas_gpio 6 0>;
};
vdd_5v0_hdmi: regulator@7 {
vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_HDMI_CON";
regulator-min-microvolt = <5000000>;

16
arch/arm/boot/dts/tegra114-roth.dts
View File

@ -801,7 +801,7 @@ regulator@43 {
};
palmas: pmic@58 {
compatible = "ti,palmas";
compatible = "ti,tps65913", "ti,palmas";
reg = <0x58>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@ -1016,7 +1016,7 @@ backlight: backlight {
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1045,7 +1045,7 @@ power {
};
};
lcd_bl_en: regulator@0 {
lcd_bl_en: regulator-lcden {
compatible = "regulator-fixed";
regulator-name = "lcd_bl_en";
regulator-min-microvolt = <5000000>;
@ -1053,7 +1053,7 @@ lcd_bl_en: regulator@0 {
regulator-boot-on;
};
vdd_lcd: regulator@1 {
vdd_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "vdd_lcd_1v8";
regulator-min-microvolt = <1800000>;
@ -1064,7 +1064,7 @@ vdd_lcd: regulator@1 {
regulator-boot-on;
};
regulator@2 {
regulator-1v8ts {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_ts";
regulator-min-microvolt = <1800000>;
@ -1073,7 +1073,7 @@ regulator@2 {
regulator-boot-on;
};
regulator@3 {
regulator-3v3ts {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_ts";
regulator-min-microvolt = <3300000>;
@ -1083,7 +1083,7 @@ regulator@3 {
regulator-boot-on;
};
regulator@4 {
regulator-1v8com {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_com";
regulator-min-microvolt = <1800000>;
@ -1094,7 +1094,7 @@ regulator@4 {
regulator-boot-on;
};
regulator@5 {
regulator-3v3com {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_com";
regulator-min-microvolt = <3300000>;

10
arch/arm/boot/dts/tegra114-tn7.dts
View File

@ -62,7 +62,7 @@ i2c@7000d000 {
clock-frequency = <400000>;
palmas: pmic@58 {
compatible = "ti,palmas";
compatible = "ti,tps65913", "ti,palmas";
reg = <0x58>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@ -273,7 +273,7 @@ backlight: backlight {
power-supply = <&lcd_bl_en>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -303,7 +303,7 @@ volume_up {
};
/* FIXME: output of BQ24192 */
vs_sys: regulator@0 {
vs_sys: regulator-vs {
compatible = "regulator-fixed";
regulator-name = "VS_SYS";
regulator-min-microvolt = <4200000>;
@ -312,7 +312,7 @@ vs_sys: regulator@0 {
regulator-boot-on;
};
lcd_bl_en: regulator@1 {
lcd_bl_en: regulator-lcden {
compatible = "regulator-fixed";
regulator-name = "VDD_LCD_BL";
regulator-min-microvolt = <16500000>;
@ -323,7 +323,7 @@ lcd_bl_en: regulator@1 {
regulator-boot-on;
};
vdd_lcd: regulator@2 {
vdd_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "VD_LCD_1V8";
regulator-min-microvolt = <1800000>;

58
arch/arm/boot/dts/tegra114.dtsi
View File

@ -17,6 +17,19 @@ memory@80000000 {
reg = <0x80000000 0x0>;
};
sram@40000000 {
compatible = "mmio-sram";
reg = <0x40000000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000000 0x40000>;
vde_pool: sram@400 {
reg = <0x400 0x3fc00>;
pool;
};
};
host1x@50000000 {
compatible = "nvidia,tegra114-host1x";
reg = <0x50000000 0x00028000>;
@ -25,8 +38,8 @@ host1x@50000000 {
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>;
reset-names = "host1x", "mc";
iommus = <&mc TEGRA_SWGROUP_HC>;
#address-cells = <1>;
@ -39,8 +52,8 @@ gr2d@54140000 {
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
reset-names = "2d", "mc";
iommus = <&mc TEGRA_SWGROUP_G2>;
};
@ -49,8 +62,8 @@ gr3d@54180000 {
compatible = "nvidia,tegra114-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
reset-names = "3d", "mc";
iommus = <&mc TEGRA_SWGROUP_NV>;
};
@ -105,7 +118,7 @@ hdmi@54280000 {
status = "disabled";
};
dsi@54300000 {
dsia: dsi@54300000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
@ -121,7 +134,7 @@ dsi@54300000 {
#size-cells = <0>;
};
dsi@54400000 {
dsib: dsi@54400000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54400000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIB>,
@ -164,7 +177,7 @@ lic: interrupt-controller@60004000 {
};
timer@60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@ -248,9 +261,31 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 246>;
*/
};
vde@6001a000 {
compatible = "nvidia,tegra114-vde";
reg = <0x6001a000 0x1000>, /* Syntax Engine */
<0x6001b000 0x1000>, /* Video Bitstream Engine */
<0x6001c000 0x100>, /* Macroblock Engine */
<0x6001c200 0x100>, /* Post-processing Engine */
<0x6001c400 0x100>, /* Motion Compensation Engine */
<0x6001c600 0x100>, /* Transform Engine */
<0x6001c800 0x100>, /* Pixel prediction block */
<0x6001ca00 0x100>, /* Video DMA */
<0x6001d800 0x400>; /* Video frame controls */
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
"tfe", "ppb", "vdma", "frameid";
iram = <&vde_pool>; /* IRAM region */
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
interrupt-names = "sync-token", "bsev", "sxe";
clocks = <&tegra_car TEGRA114_CLK_VDE>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
};
apbmisc@70000800 {
@ -542,6 +577,7 @@ mc: memory-controller@70019000 {
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
#iommu-cells = <1>;
};

436
arch/arm/boot/dts/tegra124-apalis-emc.dtsi
View File

@ -15,66 +15,77 @@ timing-12750000 {
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
clock-names = "emc-parent";
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,parent-clock-frequency = <792000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
clock-names = "emc-parent";
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,parent-clock-frequency = <528000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
clock-names = "emc-parent";
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
clock-names = "emc-parent";
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,parent-clock-frequency = <792000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
clock-names = "emc-parent";
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,parent-clock-frequency = <924000000>;
@ -84,6 +95,216 @@ timing-924000000 {
};
};
memory-controller@70019000 {
emc-timings-1 {
nvidia,ram-code = <1>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 0x8000000a
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x77e30303 0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001 0x80000012
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x76230303 0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001 0x80000017
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x74a30303 0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001 0x8000001e
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x74230403 0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001 0x80000026
0x00000001 0x00000001
0x00000003 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0503
0x73c30504 0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003 0x80000040
0x00000001 0x00000001
0x00000004 0x00000002
0x00000003 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000004 0x00000006
0x06040203 0x000a0504
0x73840a05 0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004 0x80000040
0x00000001 0x00000002
0x00000007 0x00000004
0x00000004 0x00000001
0x00000002 0x00000007
0x00000002 0x00000002
0x00000004 0x00000006
0x06040202 0x000b0607
0x77450e08 0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005 0x80000040
0x00000001 0x00000002
0x00000009 0x00000005
0x00000006 0x00000001
0x00000002 0x00000008
0x00000002 0x00000002
0x00000004 0x00000006
0x06040202 0x000d0709
0x7586120a 0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007 0x80000040
0x00000002 0x00000003
0x0000000c 0x00000007
0x00000008 0x00000001
0x00000002 0x00000009
0x00000002 0x00000002
0x00000005 0x00000006
0x06050202 0x0010090c
0x7428180d 0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009 0x80000040
0x00000003 0x00000004
0x0000000e 0x00000009
0x0000000a 0x00000001
0x00000003 0x0000000b
0x00000002 0x00000002
0x00000005 0x00000007
0x07050202 0x00130b0e
0x73a91b0f 0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b 0x80000040
0x00000004 0x00000005
0x00000013 0x0000000c
0x0000000d 0x00000002
0x00000003 0x0000000c
0x00000002 0x00000002
0x00000006 0x00000008
0x08060202 0x00170e13
0x736c2414 0x70000f02
0x001f0000
>;
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,emem-configuration = <
0x0e00000d 0x80000040
0x00000005 0x00000006
0x00000016 0x0000000e
0x0000000f 0x00000002
0x00000004 0x0000000e
0x00000002 0x00000002
0x00000006 0x00000009
0x09060202 0x001a1016
0x734e2a17 0x70000f02
0x001f0000
>;
};
};
};
external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@ -1251,225 +1472,14 @@ timing-924000000 {
0x00000011
>;
};
};
};
memory-controller@70019000 {
emc-timings-1 {
nvidia,ram-code = <1>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 0x8000000a
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x77e30303 0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001 0x80000012
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x76230303 0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001 0x80000017
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x74a30303 0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001 0x8000001e
0x00000001 0x00000001
0x00000002 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0502
0x74230403 0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001 0x80000026
0x00000001 0x00000001
0x00000003 0x00000000
0x00000002 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000003 0x00000006
0x06030203 0x000a0503
0x73c30504 0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003 0x80000040
0x00000001 0x00000001
0x00000004 0x00000002
0x00000003 0x00000001
0x00000003 0x00000008
0x00000003 0x00000002
0x00000004 0x00000006
0x06040203 0x000a0504
0x73840a05 0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004 0x80000040
0x00000001 0x00000002
0x00000007 0x00000004
0x00000004 0x00000001
0x00000002 0x00000007
0x00000002 0x00000002
0x00000004 0x00000006
0x06040202 0x000b0607
0x77450e08 0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005 0x80000040
0x00000001 0x00000002
0x00000009 0x00000005
0x00000006 0x00000001
0x00000002 0x00000008
0x00000002 0x00000002
0x00000004 0x00000006
0x06040202 0x000d0709
0x7586120a 0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007 0x80000040
0x00000002 0x00000003
0x0000000c 0x00000007
0x00000008 0x00000001
0x00000002 0x00000009
0x00000002 0x00000002
0x00000005 0x00000006
0x06050202 0x0010090c
0x7428180d 0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009 0x80000040
0x00000003 0x00000004
0x0000000e 0x00000009
0x0000000a 0x00000001
0x00000003 0x0000000b
0x00000002 0x00000002
0x00000005 0x00000007
0x07050202 0x00130b0e
0x73a91b0f 0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b 0x80000040
0x00000004 0x00000005
0x00000013 0x0000000c
0x0000000d 0x00000002
0x00000003 0x0000000c
0x00000002 0x00000002
0x00000006 0x00000008
0x08060202 0x00170e13
0x736c2414 0x70000f02
0x001f0000
>;
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,emem-configuration = <
0x0e00000d 0x80000040
0x00000005 0x00000006
0x00000016 0x0000000e
0x0000000f 0x00000002
0x00000004 0x0000000e
0x00000002 0x00000002
0x00000006 0x00000009
0x09060202 0x001a1016
0x734e2a17 0x70000f02
0x001f0000
>;
};
};
};
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@1200000000,1100;
/delete-node/ opp-1200000000-1100;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp@1200000000;
/delete-node/ opp-1200000000;
};

2
arch/arm/boot/dts/tegra124-apalis-eval.dts
View File

@ -246,7 +246,7 @@ reg_usbh_vbus: regulator-usbh-vbus {
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
pex-perst-n {
pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
output-high;

2
arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
View File

@ -248,7 +248,7 @@ reg_usbh_vbus: regulator-usbh-vbus {
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
pex-perst-n {
pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
output-high;

16
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
View File

@ -57,7 +57,7 @@ hdmi@54280000 {
};
};
gpu@0,57000000 {
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
* it after having set the VPR up
@ -1539,14 +1539,17 @@ sdmmc3-clk-lb-out-pee4 { /* NC */
serial@70006040 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006200 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
hdmi_ddc: i2c@7000c700 {
@ -1885,6 +1888,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
usb-role-switch;
vbus-supply = <&reg_usbo1_vbus>;
};
@ -2021,7 +2025,7 @@ sound {
};
thermal-zones {
cpu {
cpu-thermal {
trips {
cpu-shutdown-trip {
temperature = <101000>;
@ -2031,7 +2035,7 @@ cpu-shutdown-trip {
};
};
mem {
mem-thermal {
trips {
mem-shutdown-trip {
temperature = <101000>;
@ -2041,7 +2045,7 @@ mem-shutdown-trip {
};
};
gpu {
gpu-thermal {
trips {
gpu-shutdown-trip {
temperature = <101000>;
@ -2055,7 +2059,7 @@ gpu-shutdown-trip {
&gpio {
/* I210 Gigabit Ethernet Controller Reset */
lan-reset-n {
lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
output-high;
@ -2063,7 +2067,7 @@ lan-reset-n {
};
/* Control MXM3 pin 26 Reset Module Output Carrier Input */
reset-moci-ctrl {
reset-moci-ctrl-hog {
gpio-hog;
gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
output-high;

16
arch/arm/boot/dts/tegra124-apalis.dtsi
View File

@ -56,7 +56,7 @@ hdmi@54280000 {
};
};
gpu@0,57000000 {
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
* it after having set the VPR up
@ -1532,14 +1532,17 @@ sdmmc3-clk-lb-out-pee4 { /* NC */
serial@70006040 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006200 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
hdmi_ddc: i2c@7000c400 {
@ -1877,6 +1880,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
usb-role-switch;
vbus-supply = <&reg_usbo1_vbus>;
};
@ -2013,7 +2017,7 @@ sound {
};
thermal-zones {
cpu {
cpu-thermal {
trips {
cpu-shutdown-trip {
temperature = <101000>;
@ -2023,7 +2027,7 @@ cpu-shutdown-trip {
};
};
mem {
mem-thermal {
trips {
mem-shutdown-trip {
temperature = <101000>;
@ -2033,7 +2037,7 @@ mem-shutdown-trip {
};
};
gpu {
gpu-thermal {
trips {
gpu-shutdown-trip {
temperature = <101000>;
@ -2047,7 +2051,7 @@ gpu-shutdown-trip {
&gpio {
/* I210 Gigabit Ethernet Controller Reset */
lan-reset-n {
lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
output-high;
@ -2055,7 +2059,7 @@ lan-reset-n {
};
/* Control MXM3 pin 26 Reset Module Output Carrier Input */
reset-moci-ctrl {
reset-moci-ctrl-hog {
gpio-hog;
gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
output-high;

652
arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
View File

@ -10,66 +10,77 @@ timing-12750000 {
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
clock-names = "emc-parent";
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,parent-clock-frequency = <792000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
clock-names = "emc-parent";
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,parent-clock-frequency = <528000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
clock-names = "emc-parent";
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
clock-names = "emc-parent";
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,parent-clock-frequency = <792000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
clock-names = "emc-parent";
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,parent-clock-frequency = <924000000>;
@ -79,6 +90,324 @@ timing-924000000 {
};
};
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001
0x8000000a
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x77e30303
0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001
0x80000012
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x76230303
0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001
0x80000017
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x74a30303
0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001
0x8000001e
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x74230403
0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001
0x80000026
0x00000001
0x00000001
0x00000003
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0503
0x73c30504
0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003
0x80000040
0x00000001
0x00000001
0x00000004
0x00000002
0x00000003
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000004
0x00000006
0x06040203
0x000a0504
0x73840a05
0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004
0x80000040
0x00000001
0x00000002
0x00000007
0x00000004
0x00000004
0x00000001
0x00000002
0x00000007
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000b0607
0x77450e08
0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005
0x80000040
0x00000001
0x00000002
0x00000009
0x00000005
0x00000006
0x00000001
0x00000002
0x00000008
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000d0709
0x7586120a
0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007
0x80000040
0x00000002
0x00000003
0x0000000c
0x00000007
0x00000008
0x00000001
0x00000002
0x00000009
0x00000002
0x00000002
0x00000005
0x00000006
0x06050202
0x0010090c
0x7428180d
0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009
0x80000040
0x00000003
0x00000004
0x0000000e
0x00000009
0x0000000a
0x00000001
0x00000003
0x0000000b
0x00000002
0x00000002
0x00000005
0x00000007
0x07050202
0x00130b0e
0x73a91b0f
0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b
0x80000040
0x00000004
0x00000005
0x00000013
0x0000000c
0x0000000d
0x00000002
0x00000003
0x0000000c
0x00000002
0x00000002
0x00000006
0x00000008
0x08060202
0x00170e13
0x736c2414
0x70000f02
0x001f0000
>;
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,emem-configuration = <
0x0e00000d
0x80000040
0x00000005
0x00000006
0x00000016
0x0000000e
0x0000000f
0x00000002
0x00000004
0x0000000e
0x00000002
0x00000002
0x00000006
0x00000009
0x09060202
0x001a1016
0x734e2a17
0x70000f02
0x001f0000
>;
};
};
};
external-memory-controller@7001b000 {
emc-timings-3 {
nvidia,ram-code = <3>;
@ -2098,333 +2427,14 @@ timing-924000000 {
0x00000011
>;
};
};
};
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001
0x8000000a
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x77e30303
0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001
0x80000012
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x76230303
0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001
0x80000017
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x74a30303
0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001
0x8000001e
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0502
0x74230403
0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001
0x80000026
0x00000001
0x00000001
0x00000003
0x00000000
0x00000002
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0503
0x73c30504
0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003
0x80000040
0x00000001
0x00000001
0x00000004
0x00000002
0x00000003
0x00000001
0x00000003
0x00000008
0x00000003
0x00000002
0x00000004
0x00000006
0x06040203
0x000a0504
0x73840a05
0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004
0x80000040
0x00000001
0x00000002
0x00000007
0x00000004
0x00000004
0x00000001
0x00000002
0x00000007
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000b0607
0x77450e08
0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005
0x80000040
0x00000001
0x00000002
0x00000009
0x00000005
0x00000006
0x00000001
0x00000002
0x00000008
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000d0709
0x7586120a
0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007
0x80000040
0x00000002
0x00000003
0x0000000c
0x00000007
0x00000008
0x00000001
0x00000002
0x00000009
0x00000002
0x00000002
0x00000005
0x00000006
0x06050202
0x0010090c
0x7428180d
0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009
0x80000040
0x00000003
0x00000004
0x0000000e
0x00000009
0x0000000a
0x00000001
0x00000003
0x0000000b
0x00000002
0x00000002
0x00000005
0x00000007
0x07050202
0x00130b0e
0x73a91b0f
0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b
0x80000040
0x00000004
0x00000005
0x00000013
0x0000000c
0x0000000d
0x00000002
0x00000003
0x0000000c
0x00000002
0x00000002
0x00000006
0x00000008
0x08060202
0x00170e13
0x736c2414
0x70000f02
0x001f0000
>;
};
timing-924000000 {
clock-frequency = <924000000>;
nvidia,emem-configuration = <
0x0e00000d
0x80000040
0x00000005
0x00000006
0x00000016
0x0000000e
0x0000000f
0x00000002
0x00000004
0x0000000e
0x00000002
0x00000002
0x00000006
0x00000009
0x09060202
0x001a1016
0x734e2a17
0x70000f02
0x001f0000
>;
};
};
};
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@1200000000,1100;
/delete-node/ opp-1200000000-1100;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp@1200000000;
/delete-node/ opp-1200000000;
};

39
arch/arm/boot/dts/tegra124-jetson-tk1.dts
View File

@ -72,7 +72,7 @@ cec@70015000 {
status = "okay";
};
gpu@0,57000000 {
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
* it after having set the VPR up
@ -1389,6 +1389,7 @@ dsi_b {
*/
serial@70006000 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
status = "okay";
};
@ -1401,6 +1402,7 @@ serial@70006000 {
*/
serial@70006040 {
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
status = "okay";
};
@ -1655,7 +1657,8 @@ spi@7000d400 {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@0 {
flash@0 {
compatible = "winbond,w25q32dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
@ -1868,7 +1871,7 @@ usb-phy@7d008000 {
vbus-supply = <&vdd_usb3_vbus>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1892,7 +1895,7 @@ power {
};
};
vdd_mux: regulator@0 {
vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@ -1901,7 +1904,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@ -1911,7 +1914,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@ -1921,7 +1924,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@ -1933,7 +1936,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
vdd_3v3_hdmi: regulator-3v3hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@ -1941,7 +1944,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
vdd_usb1_vbus: regulator@5 {
vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+USB0_VBUS_SW";
regulator-min-microvolt = <5000000>;
@ -1952,7 +1955,7 @@ vdd_usb1_vbus: regulator@5 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@6 {
vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@ -1963,7 +1966,7 @@ vdd_usb3_vbus: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_lp0: regulator@7 {
vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@ -1975,7 +1978,7 @@ vdd_3v3_lp0: regulator@7 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@8 {
vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@ -1984,7 +1987,7 @@ vdd_hdmi_pll: regulator@8 {
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@9 {
vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -1995,7 +1998,7 @@ vdd_5v0_hdmi: regulator@9 {
};
/* Molex power connector */
vdd_5v0_sata: regulator@10 {
vdd_5v0_sata: regulator-5v0sata {
compatible = "regulator-fixed";
regulator-name = "+5V_SATA";
regulator-min-microvolt = <5000000>;
@ -2005,7 +2008,7 @@ vdd_5v0_sata: regulator@10 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_12v0_sata: regulator@11 {
vdd_12v0_sata: regulator-12v0sata {
compatible = "regulator-fixed";
regulator-name = "+12V_SATA";
regulator-min-microvolt = <12000000>;
@ -2044,7 +2047,7 @@ sound {
};
thermal-zones {
cpu {
cpu-thermal {
trips {
cpu-shutdown-trip {
temperature = <101000>;
@ -2054,7 +2057,7 @@ cpu-shutdown-trip {
};
};
mem {
mem-thermal {
trips {
mem-shutdown-trip {
temperature = <101000>;
@ -2064,7 +2067,7 @@ mem-shutdown-trip {
};
};
gpu {
gpu-thermal {
trips {
gpu-shutdown-trip {
temperature = <101000>;

1782
arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
View File

File diff suppressed because it is too large Load Diff

11
arch/arm/boot/dts/tegra124-nyan-big-fhd.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra124-nyan-big.dts"
/ {
/* Version of Nyan Big with 1080p panel */
panel {
compatible = "auo,b133htn01";
};
};

604
arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
View File

@ -10,55 +10,65 @@ timing-12750000 {
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
clock-names = "emc-parent";
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,parent-clock-frequency = <792000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
clock-names = "emc-parent";
};
/* TODO: Add 528MHz frequency */
timing-600000000 {
clock-frequency = <600000000>;
nvidia,parent-clock-frequency = <600000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
clock-names = "emc-parent";
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,parent-clock-frequency = <792000000>;
@ -68,6 +78,298 @@ timing-792000000 {
};
};
memory-controller@70019000 {
emc-timings-1 {
nvidia,ram-code = <1>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001
0x8000000a
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x77e30303
0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001
0x80000012
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x76230303
0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001
0x80000017
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x74a30303
0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001
0x8000001e
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x74230403
0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001
0x80000026
0x00000001
0x00000001
0x00000003
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0403
0x73c30504
0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003
0x80000040
0x00000001
0x00000001
0x00000005
0x00000002
0x00000004
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000004
0x00000006
0x06040203
0x000a0405
0x73840a06
0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004
0x80000040
0x00000001
0x00000002
0x00000007
0x00000004
0x00000005
0x00000001
0x00000002
0x00000007
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000b0607
0x77450e08
0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005
0x80000040
0x00000001
0x00000002
0x00000009
0x00000005
0x00000007
0x00000001
0x00000002
0x00000008
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000d0709
0x7586120a
0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007
0x80000040
0x00000002
0x00000003
0x0000000d
0x00000008
0x0000000a
0x00000001
0x00000002
0x00000009
0x00000002
0x00000002
0x00000005
0x00000006
0x06050202
0x0010090d
0x7428180e
0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009
0x80000040
0x00000003
0x00000004
0x0000000e
0x00000009
0x0000000b
0x00000001
0x00000003
0x0000000b
0x00000002
0x00000002
0x00000005
0x00000007
0x07050202
0x00130b0e
0x73a91b0f
0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b
0x80000040
0x00000004
0x00000005
0x00000013
0x0000000c
0x0000000f
0x00000002
0x00000003
0x0000000c
0x00000002
0x00000002
0x00000006
0x00000008
0x08060202
0x00160d13
0x734c2414
0x70000f02
0x001f0000
>;
};
};
};
external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@ -1751,310 +2053,16 @@ timing-792000000 {
0x0000000f
>;
};
};
};
memory-controller@70019000 {
emc-timings-1 {
nvidia,ram-code = <1>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001
0x8000000a
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x77e30303
0x70000f03
0x001f0000
>;
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,emem-configuration = <
0x40020001
0x80000012
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x76230303
0x70000f03
0x001f0000
>;
};
timing-40800000 {
clock-frequency = <40800000>;
nvidia,emem-configuration = <
0xa0000001
0x80000017
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x74a30303
0x70000f03
0x001f0000
>;
};
timing-68000000 {
clock-frequency = <68000000>;
nvidia,emem-configuration = <
0x00000001
0x8000001e
0x00000001
0x00000001
0x00000002
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0402
0x74230403
0x70000f03
0x001f0000
>;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = <
0x08000001
0x80000026
0x00000001
0x00000001
0x00000003
0x00000000
0x00000002
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000003
0x00000006
0x06030203
0x000a0403
0x73c30504
0x70000f03
0x001f0000
>;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = <
0x01000003
0x80000040
0x00000001
0x00000001
0x00000005
0x00000002
0x00000004
0x00000001
0x00000002
0x00000008
0x00000003
0x00000002
0x00000004
0x00000006
0x06040203
0x000a0405
0x73840a06
0x70000f03
0x001f0000
>;
};
timing-300000000 {
clock-frequency = <300000000>;
nvidia,emem-configuration = <
0x08000004
0x80000040
0x00000001
0x00000002
0x00000007
0x00000004
0x00000005
0x00000001
0x00000002
0x00000007
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000b0607
0x77450e08
0x70000f03
0x001f0000
>;
};
timing-396000000 {
clock-frequency = <396000000>;
nvidia,emem-configuration = <
0x0f000005
0x80000040
0x00000001
0x00000002
0x00000009
0x00000005
0x00000007
0x00000001
0x00000002
0x00000008
0x00000002
0x00000002
0x00000004
0x00000006
0x06040202
0x000d0709
0x7586120a
0x70000f03
0x001f0000
>;
};
timing-528000000 {
clock-frequency = <528000000>;
nvidia,emem-configuration = <
0x0f000007
0x80000040
0x00000002
0x00000003
0x0000000d
0x00000008
0x0000000a
0x00000001
0x00000002
0x00000009
0x00000002
0x00000002
0x00000005
0x00000006
0x06050202
0x0010090d
0x7428180e
0x70000f03
0x001f0000
>;
};
timing-600000000 {
clock-frequency = <600000000>;
nvidia,emem-configuration = <
0x00000009
0x80000040
0x00000003
0x00000004
0x0000000e
0x00000009
0x0000000b
0x00000001
0x00000003
0x0000000b
0x00000002
0x00000002
0x00000005
0x00000007
0x07050202
0x00130b0e
0x73a91b0f
0x70000f03
0x001f0000
>;
};
timing-792000000 {
clock-frequency = <792000000>;
nvidia,emem-configuration = <
0x0e00000b
0x80000040
0x00000004
0x00000005
0x00000013
0x0000000c
0x0000000f
0x00000002
0x00000003
0x0000000c
0x00000002
0x00000002
0x00000006
0x00000008
0x08060202
0x00160d13
0x734c2414
0x70000f02
0x001f0000
>;
};
};
};
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@924000000,1100;
/delete-node/ opp@1200000000,1100;
/delete-node/ opp-924000000-1100;
/delete-node/ opp-1200000000-1100;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp@924000000;
/delete-node/ opp@1200000000;
/delete-node/ opp-924000000;
/delete-node/ opp-1200000000;
};

86
arch/arm/boot/dts/tegra124-nyan.dtsi
View File

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "tegra124.dtsi"
/ {
@ -61,7 +62,7 @@ dpaux@545c0000 {
};
};
gpu@0,57000000 {
gpu@57000000 {
status = "okay";
vdd-supply = <&vdd_gpu>;
@ -87,7 +88,7 @@ acodec: audio-codec@10 {
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
};
temperature-sensor@4c {
tmp451: temperature-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
interrupt-parent = <&gpio>;
@ -390,6 +391,10 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
cec@70015000 {
status = "okay";
};
hda@70030000 {
status = "okay";
};
@ -466,6 +471,7 @@ usb2-0 {
vbus-supply = <&vdd_usb1_vbus>;
status = "okay";
mode = "otg";
usb-role-switch;
};
usb2-1 {
@ -527,7 +533,7 @@ mmc@700b0600 { /* eMMC on this bus */
/* CPU DFLL clock */
clock@70110000 {
status = "disabled";
status = "okay";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
};
@ -582,7 +588,7 @@ backlight: backlight {
256>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -615,7 +621,7 @@ power {
};
};
vdd_mux: regulator@0 {
vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@ -624,7 +630,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@ -634,7 +640,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@ -644,7 +650,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@ -656,7 +662,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
vdd_3v3_hdmi: regulator-3v3hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@ -664,7 +670,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
vdd_led: regulator@5 {
vdd_led: regulator-led {
compatible = "regulator-fixed";
regulator-name = "+VDD_LED";
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
@ -672,7 +678,7 @@ vdd_led: regulator@5 {
vin-supply = <&vdd_mux>;
};
vdd_5v0_ts: regulator@6 {
vdd_5v0_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "+5V_VDD_TS_SW";
regulator-min-microvolt = <5000000>;
@ -683,7 +689,7 @@ vdd_5v0_ts: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb1_vbus: regulator@7 {
vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@ -694,7 +700,7 @@ vdd_usb1_vbus: regulator@7 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@8 {
vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
@ -705,7 +711,7 @@ vdd_usb3_vbus: regulator@8 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_panel: regulator@9 {
vdd_3v3_panel: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
@ -715,7 +721,7 @@ vdd_3v3_panel: regulator@9 {
vin-supply = <&vdd_3v3_run>;
};
vdd_3v3_lp0: regulator@10 {
vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@ -730,7 +736,7 @@ vdd_3v3_lp0: regulator@10 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@11 {
vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@ -739,7 +745,7 @@ vdd_hdmi_pll: regulator@11 {
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@12 {
vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -784,6 +790,52 @@ gpio-restart {
gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
priority = <200>;
};
cpus {
cpu0: cpu@0 {
#cooling-cells = <2>;
};
cpu1: cpu@1 {
#cooling-cells = <2>;
};
cpu2: cpu@2 {
#cooling-cells = <2>;
};
cpu3: cpu@3 {
#cooling-cells = <2>;
};
};
thermal-zones {
cpu-skin-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tmp451 0>;
trips {
cpu_passive_trip: cpu-alert0 {
/* throttle at 70C until temperature drops to 69.8C */
temperature = <70000>;
hysteresis = <200>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_passive_trip>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
#include "cros-ec-keyboard.dtsi"

140
arch/arm/boot/dts/tegra124-peripherals-opp.dtsi
View File

@ -1,421 +1,421 @@
// SPDX-License-Identifier: GPL-2.0
/ {
emc_icc_dvfs_opp_table: emc-dvfs-opp-table {
emc_icc_dvfs_opp_table: opp-table-emc {
compatible = "operating-points-v2";
opp@12750000,800 {
opp-12750000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0003>;
};
opp@12750000,950 {
opp-12750000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0008>;
};
opp@12750000,1050 {
opp-12750000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0010>;
};
opp@12750000,1110 {
opp-12750000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0004>;
};
opp@20400000,800 {
opp-20400000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0003>;
};
opp@20400000,950 {
opp-20400000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0008>;
};
opp@20400000,1050 {
opp-20400000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0010>;
};
opp@20400000,1110 {
opp-20400000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0004>;
};
opp@40800000,800 {
opp-40800000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0003>;
};
opp@40800000,950 {
opp-40800000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0008>;
};
opp@40800000,1050 {
opp-40800000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0010>;
};
opp@40800000,1110 {
opp-40800000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0004>;
};
opp@68000000,800 {
opp-68000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0003>;
};
opp@68000000,950 {
opp-68000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0008>;
};
opp@68000000,1050 {
opp-68000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0010>;
};
opp@68000000,1110 {
opp-68000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0004>;
};
opp@102000000,800 {
opp-102000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0003>;
};
opp@102000000,950 {
opp-102000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0008>;
};
opp@102000000,1050 {
opp-102000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0010>;
};
opp@102000000,1110 {
opp-102000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0004>;
};
opp@204000000,800 {
opp-204000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0003>;
opp-suspend;
};
opp@204000000,950 {
opp-204000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0008>;
opp-suspend;
};
opp@204000000,1050 {
opp-204000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0010>;
opp-suspend;
};
opp@204000000,1110 {
opp-204000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0004>;
opp-suspend;
};
opp@264000000,800 {
opp-264000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0003>;
};
opp@264000000,950 {
opp-264000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0008>;
};
opp@264000000,1050 {
opp-264000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0010>;
};
opp@264000000,1110 {
opp-264000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0004>;
};
opp@300000000,850 {
opp-300000000-850 {
opp-microvolt = <850000 850000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0003>;
};
opp@300000000,950 {
opp-300000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0008>;
};
opp@300000000,1050 {
opp-300000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0010>;
};
opp@300000000,1110 {
opp-300000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0004>;
};
opp@348000000,850 {
opp-348000000-850 {
opp-microvolt = <850000 850000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0003>;
};
opp@348000000,950 {
opp-348000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0008>;
};
opp@348000000,1050 {
opp-348000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0010>;
};
opp@348000000,1110 {
opp-348000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0004>;
};
opp@396000000,950 {
opp-396000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0008>;
};
opp@396000000,1000 {
opp-396000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0003>;
};
opp@396000000,1050 {
opp-396000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0010>;
};
opp@396000000,1110 {
opp-396000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0004>;
};
opp@528000000,950 {
opp-528000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0008>;
};
opp@528000000,1000 {
opp-528000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0003>;
};
opp@528000000,1050 {
opp-528000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0010>;
};
opp@528000000,1110 {
opp-528000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0004>;
};
opp@600000000,950 {
opp-600000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0008>;
};
opp@600000000,1000 {
opp-600000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0003>;
};
opp@600000000,1050 {
opp-600000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0010>;
};
opp@600000000,1110 {
opp-600000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0004>;
};
opp@792000000,1000 {
opp-792000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x000B>;
};
opp@792000000,1050 {
opp-792000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x0010>;
};
opp@792000000,1110 {
opp-792000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x0004>;
};
opp@924000000,1100 {
opp-924000000-1100 {
opp-microvolt = <1100000 1100000 1150000>;
opp-hz = /bits/ 64 <924000000>;
opp-supported-hw = <0x0013>;
};
opp@1200000000,1100 {
opp-1200000000-1100 {
opp-microvolt = <1100000 1100000 1150000>;
opp-hz = /bits/ 64 <1200000000>;
opp-supported-hw = <0x0003>;
};
};
emc_bw_dfs_opp_table: emc-bandwidth-opp-table {
emc_bw_dfs_opp_table: opp-table-actmon {
compatible = "operating-points-v2";
opp@12750000 {
opp-12750000 {
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <204000>;
};
opp@20400000 {
opp-20400000 {
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <326400>;
};
opp@40800000 {
opp-40800000 {
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <652800>;
};
opp@68000000 {
opp-68000000 {
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <1088000>;
};
opp@102000000 {
opp-102000000 {
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <1632000>;
};
opp@204000000 {
opp-204000000 {
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <3264000>;
opp-suspend;
};
opp@264000000 {
opp-264000000 {
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <4224000>;
};
opp@300000000 {
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <4800000>;
};
opp@348000000 {
opp-348000000 {
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <5568000>;
};
opp@396000000 {
opp-396000000 {
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <6336000>;
};
opp@528000000 {
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <8448000>;
};
opp@600000000 {
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <9600000>;
};
opp@792000000 {
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <12672000>;
};
opp@924000000 {
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-supported-hw = <0x0013>;
opp-peak-kBps = <14784000>;
};
opp@1200000000 {
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <19200000>;

35
arch/arm/boot/dts/tegra124-venice2.dts
View File

@ -51,7 +51,7 @@ dpaux@545c0000 {
};
};
gpu@0,57000000 {
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
* it after having set the VPR up
@ -881,7 +881,8 @@ battery: sbs-battery@b {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@0 {
flash@0 {
compatible = "winbond,w25q32dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
@ -972,7 +973,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
usb-role-switch;
vbus-supply = <&vdd_usb1_vbus>;
};
@ -1061,7 +1062,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1086,7 +1087,7 @@ panel: panel {
ddc-i2c-bus = <&dpaux>;
};
vdd_mux: regulator@0 {
vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@ -1095,7 +1096,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@ -1105,7 +1106,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@ -1115,7 +1116,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@ -1127,7 +1128,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
vdd_3v3_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@ -1135,7 +1136,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
vdd_led: regulator@5 {
vdd_led: regulator-led {
compatible = "regulator-fixed";
regulator-name = "+VDD_LED";
regulator-min-microvolt = <3300000>;
@ -1145,7 +1146,7 @@ vdd_led: regulator@5 {
vin-supply = <&vdd_mux>;
};
vdd_5v0_ts: regulator@6 {
vdd_5v0_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "+5V_VDD_TS_SW";
regulator-min-microvolt = <5000000>;
@ -1156,7 +1157,7 @@ vdd_5v0_ts: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb1_vbus: regulator@7 {
vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@ -1167,7 +1168,7 @@ vdd_usb1_vbus: regulator@7 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@8 {
vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
@ -1178,7 +1179,7 @@ vdd_usb3_vbus: regulator@8 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_panel: regulator@9 {
vdd_3v3_panel: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
@ -1188,7 +1189,7 @@ vdd_3v3_panel: regulator@9 {
vin-supply = <&vdd_3v3_run>;
};
vdd_3v3_lp0: regulator@10 {
vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@ -1203,7 +1204,7 @@ vdd_3v3_lp0: regulator@10 {
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@11 {
vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@ -1212,7 +1213,7 @@ vdd_hdmi_pll: regulator@11 {
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@12 {
vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;

45
arch/arm/boot/dts/tegra124.dtsi
View File

@ -94,8 +94,8 @@ host1x@50000000 {
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>;
reset-names = "host1x", "mc";
iommus = <&mc TEGRA_SWGROUP_HC>;
#address-cells = <2>;
@ -223,12 +223,7 @@ gic: interrupt-controller@50041000 {
interrupt-parent = <&gic>;
};
/*
* Please keep the following 0, notation in place as a former mainline
* U-Boot version was looking for that particular notation in order to
* perform required fix-ups on that GPU node.
*/
gpu@0,57000000 {
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
@ -259,7 +254,7 @@ lic: interrupt-controller@60004000 {
};
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@ -313,9 +308,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 251>;
*/
};
apbdma: dma@60020000 {
@ -443,7 +436,7 @@ pwm: pwm@7000a000 {
};
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -458,7 +451,7 @@ i2c@7000c000 {
};
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -473,7 +466,7 @@ i2c@7000c400 {
};
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -488,7 +481,7 @@ i2c@7000c500 {
};
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -503,7 +496,7 @@ i2c@7000c700 {
};
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -518,7 +511,7 @@ i2c@7000d000 {
};
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -677,10 +670,8 @@ sata@70020000 {
<0x0 0x70020000 0x0 0x7000>; /* SATA */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SATA>,
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
<&tegra_car TEGRA124_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
resets = <&tegra_car 124>,
<&tegra_car 129>,
<&tegra_car 123>;
@ -717,8 +708,8 @@ usb@70090000 {
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
@ -726,7 +717,7 @@ usb@70090000 {
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_src", "xusb_ss_div2",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
@ -1247,7 +1238,7 @@ pmu {
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
@ -1275,7 +1266,7 @@ map0 {
};
};
mem {
mem-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
@ -1303,7 +1294,7 @@ cooling-maps {
};
};
gpu {
gpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
@ -1331,7 +1322,7 @@ map0 {
};
};
pllx {
pllx-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;

27
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
View File

@ -376,17 +376,27 @@ pta {
};
};
tegra_spdif: spdif@70002400 {
status = "okay";
nvidia,fixed-parent-rate;
};
tegra_i2s1: i2s@70002800 {
status = "okay";
nvidia,fixed-parent-rate;
};
uartb: serial@70006040 {
compatible = "nvidia,tegra20-hsuart";
/delete-property/ reg-shift;
/* GPS BCM4751 */
};
uartc: serial@70006200 {
compatible = "nvidia,tegra20-hsuart";
/delete-property/ reg-shift;
status = "okay";
/* Azurewave AW-NH665 BCM4329B1 */
@ -716,6 +726,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
usb@c5000000 {
@ -827,7 +838,7 @@ bat1010: battery-2s1p {
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock@0 {
clk32k_in: clock-32k-in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@ -839,7 +850,7 @@ clk32k_in: clock@0 {
* oscillator is used as a reference clock-source by the
* Azurewave WiFi/BT module.
*/
rtc_32k_wifi: clock@1 {
rtc_32k_wifi: clock-32k-wifi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@ -964,7 +975,7 @@ lvds_encoder_output: endpoint {
};
};
vdd_5v0_sys: regulator@0 {
vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@ -972,7 +983,7 @@ vdd_5v0_sys: regulator@0 {
regulator-always-on;
};
vdd_3v3_sys: regulator@1 {
vdd_3v3_sys: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_vs";
regulator-min-microvolt = <3300000>;
@ -981,7 +992,7 @@ vdd_3v3_sys: regulator@1 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_1v8_sys: regulator@2 {
vdd_1v8_sys: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_vs";
regulator-min-microvolt = <1800000>;
@ -990,7 +1001,7 @@ vdd_1v8_sys: regulator@2 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_pnl: regulator@3 {
vdd_pnl: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
@ -1506,6 +1517,6 @@ emc-table@300000 {
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@666000000;
/delete-node/ opp@760000000;
/delete-node/ opp-666000000;
/delete-node/ opp-760000000;
};

1280
arch/arm/boot/dts/tegra20-asus-tf101.dts Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
View File

@ -70,11 +70,11 @@ mmccd {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwm-a-b {
sdc {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwm-c-d {
sdb_sdd {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};

4
arch/arm/boot/dts/tegra20-colibri-iris.dts
View File

@ -70,11 +70,11 @@ mmccd {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwm-a-b {
sdc {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwm-c-d {
sdb_sdd {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};

18
arch/arm/boot/dts/tegra20-colibri.dtsi
View File

@ -113,7 +113,7 @@ bl-on {
};
/* Colibri Backlight PWM<A>, PWM<B> */
pwm-a-b {
sdc {
nvidia,pins = "sdc";
nvidia,function = "pwm";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
@ -242,7 +242,7 @@ cif {
};
/* Colibri PWM<C>, PWM<D> */
pwm-c-d {
sdb_sdd {
nvidia,pins = "sdb", "sdd";
nvidia,function = "pwm";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
@ -428,10 +428,12 @@ tegra_ac97: ac97@70002000 {
serial@70006040 {
compatible = "nvidia,tegra20-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra20-hsuart";
/delete-property/ reg-shift;
};
nand-controller@70008000 {
@ -495,7 +497,7 @@ reg_3v3_vsys: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "VDD_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -601,6 +603,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
i2c-thermtrip {
@ -689,6 +692,7 @@ usb@c5004000 {
#size-cells = <0>;
asix@1 {
compatible = "usbb95,772b";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
@ -743,11 +747,11 @@ sound {
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@760000000;
/delete-node/ opp-760000000;
};
&gpio {
lan-reset-n {
lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
output-high;
@ -755,7 +759,7 @@ lan-reset-n {
};
/* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
npwe {
npwe-hog {
gpio-hog;
gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
output-high;
@ -763,7 +767,7 @@ npwe {
};
/* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
rdnwr {
rdnwr-hog {
gpio-hog;
gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
output-low;

82
arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
View File

@ -1,164 +1,164 @@
// SPDX-License-Identifier: GPL-2.0
/ {
cpu0_opp_table: cpu_opp_table0 {
opp@216000000,750 {
cpu0_opp_table: opp-table-cpu0 {
opp-216000000-750 {
opp-microvolt = <750000 750000 1125000>;
};
opp@216000000,800 {
opp-216000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@312000000,750 {
opp-312000000-750 {
opp-microvolt = <750000 750000 1125000>;
};
opp@312000000,800 {
opp-312000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@456000000,750 {
opp-456000000-750 {
opp-microvolt = <750000 750000 1125000>;
};
opp@456000000,800 {
opp-456000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@456000000,825 {
opp-456000000-825 {
opp-microvolt = <825000 825000 1125000>;
};
opp@608000000,750 {
opp-608000000-750 {
opp-microvolt = <750000 750000 1125000>;
};
opp@608000000,800 {
opp-608000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@608000000,825 {
opp-608000000-825 {
opp-microvolt = <825000 825000 1125000>;
};
opp@608000000,850 {
opp-608000000-850 {
opp-microvolt = <850000 850000 1125000>;
};
opp@608000000,900 {
opp-608000000-900 {
opp-microvolt = <900000 900000 1125000>;
};
opp@760000000,775 {
opp-760000000-775 {
opp-microvolt = <775000 775000 1125000>;
};
opp@760000000,800 {
opp-760000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@760000000,850 {
opp-760000000-850 {
opp-microvolt = <850000 850000 1125000>;
};
opp@760000000,875 {
opp-760000000-875 {
opp-microvolt = <875000 875000 1125000>;
};
opp@760000000,900 {
opp-760000000-900 {
opp-microvolt = <900000 900000 1125000>;
};
opp@760000000,975 {
opp-760000000-975 {
opp-microvolt = <975000 975000 1125000>;
};
opp@816000000,800 {
opp-816000000-800 {
opp-microvolt = <800000 800000 1125000>;
};
opp@816000000,850 {
opp-816000000-850 {
opp-microvolt = <850000 850000 1125000>;
};
opp@816000000,875 {
opp-816000000-875 {
opp-microvolt = <875000 875000 1125000>;
};
opp@816000000,950 {
opp-816000000-950 {
opp-microvolt = <950000 950000 1125000>;
};
opp@816000000,1000 {
opp-816000000-1000 {
opp-microvolt = <1000000 1000000 1125000>;
};
opp@912000000,850 {
opp-912000000-850 {
opp-microvolt = <850000 850000 1125000>;
};
opp@912000000,900 {
opp-912000000-900 {
opp-microvolt = <900000 900000 1125000>;
};
opp@912000000,925 {
opp-912000000-925 {
opp-microvolt = <925000 925000 1125000>;
};
opp@912000000,950 {
opp-912000000-950 {
opp-microvolt = <950000 950000 1125000>;
};
opp@912000000,1000 {
opp-912000000-1000 {
opp-microvolt = <1000000 1000000 1125000>;
};
opp@912000000,1050 {
opp-912000000-1050 {
opp-microvolt = <1050000 1050000 1125000>;
};
opp@1000000000,875 {
opp-1000000000-875 {
opp-microvolt = <875000 875000 1125000>;
};
opp@1000000000,900 {
opp-1000000000-900 {
opp-microvolt = <900000 900000 1125000>;
};
opp@1000000000,950 {
opp-1000000000-950 {
opp-microvolt = <950000 950000 1125000>;
};
opp@1000000000,975 {
opp-1000000000-975 {
opp-microvolt = <975000 975000 1125000>;
};
opp@1000000000,1000 {
opp-1000000000-1000 {
opp-microvolt = <1000000 1000000 1125000>;
};
opp@1000000000,1025 {
opp-1000000000-1025 {
opp-microvolt = <1025000 1025000 1125000>;
};
opp@1000000000,1100 {
opp-1000000000-1100 {
opp-microvolt = <1100000 1100000 1125000>;
};
opp@1200000000,1000 {
opp-1200000000-1000 {
opp-microvolt = <1000000 1000000 1125000>;
};
opp@1200000000,1050 {
opp-1200000000-1050 {
opp-microvolt = <1050000 1050000 1125000>;
};
opp@1200000000,1100 {
opp-1200000000-1100 {
opp-microvolt = <1100000 1100000 1125000>;
};
opp@1200000000,1125 {
opp-1200000000-1125 {
opp-microvolt = <1125000 1125000 1125000>;
};
};

82
arch/arm/boot/dts/tegra20-cpu-opp.dtsi
View File

@ -1,250 +1,250 @@
// SPDX-License-Identifier: GPL-2.0
/ {
cpu0_opp_table: cpu_opp_table0 {
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
opp@216000000,750 {
opp-216000000-750 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0003>;
opp-hz = /bits/ 64 <216000000>;
opp-suspend;
};
opp@216000000,800 {
opp-216000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0004>;
opp-hz = /bits/ 64 <216000000>;
opp-suspend;
};
opp@312000000,750 {
opp-312000000-750 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0003>;
opp-hz = /bits/ 64 <312000000>;
};
opp@312000000,800 {
opp-312000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0004>;
opp-hz = /bits/ 64 <312000000>;
};
opp@456000000,750 {
opp-456000000-750 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0C 0x0003>;
opp-hz = /bits/ 64 <456000000>;
};
opp@456000000,800 {
opp-456000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>,
<0x08 0x0004>;
opp-hz = /bits/ 64 <456000000>;
};
opp@456000000,825 {
opp-456000000-825 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <456000000>;
};
opp@608000000,750 {
opp-608000000-750 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0003>;
opp-hz = /bits/ 64 <608000000>;
};
opp@608000000,800 {
opp-608000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>;
opp-hz = /bits/ 64 <608000000>;
};
opp@608000000,825 {
opp-608000000-825 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0001>;
opp-hz = /bits/ 64 <608000000>;
};
opp@608000000,850 {
opp-608000000-850 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0006>;
opp-hz = /bits/ 64 <608000000>;
};
opp@608000000,900 {
opp-608000000-900 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <608000000>;
};
opp@760000000,775 {
opp-760000000-775 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0003>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,800 {
opp-760000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0004>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,850 {
opp-760000000-850 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0006>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,875 {
opp-760000000-875 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>,
<0x01 0x0004>, <0x02 0x0004>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,900 {
opp-760000000-900 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x01 0x0002>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,975 {
opp-760000000-975 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <760000000>;
};
opp@816000000,800 {
opp-816000000-800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0007>;
opp-hz = /bits/ 64 <816000000>;
};
opp@816000000,850 {
opp-816000000-850 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0002>;
opp-hz = /bits/ 64 <816000000>;
};
opp@816000000,875 {
opp-816000000-875 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0005>;
opp-hz = /bits/ 64 <816000000>;
};
opp@816000000,950 {
opp-816000000-950 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0006>;
opp-hz = /bits/ 64 <816000000>;
};
opp@816000000,1000 {
opp-816000000-1000 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <816000000>;
};
opp@912000000,850 {
opp-912000000-850 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0007>;
opp-hz = /bits/ 64 <912000000>;
};
opp@912000000,900 {
opp-912000000-900 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0002>;
opp-hz = /bits/ 64 <912000000>;
};
opp@912000000,925 {
opp-912000000-925 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0001>;
opp-hz = /bits/ 64 <912000000>;
};
opp@912000000,950 {
opp-912000000-950 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>,
<0x04 0x0004>;
opp-hz = /bits/ 64 <912000000>;
};
opp@912000000,1000 {
opp-912000000-1000 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x01 0x0002>;
opp-hz = /bits/ 64 <912000000>;
};
opp@912000000,1050 {
opp-912000000-1050 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <912000000>;
};
opp@1000000000,875 {
opp-1000000000-875 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0007>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,900 {
opp-1000000000-900 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0002>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,950 {
opp-1000000000-950 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0004>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,975 {
opp-1000000000-975 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0001>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,1000 {
opp-1000000000-1000 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,1025 {
opp-1000000000-1025 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x01 0x0002>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,1100 {
opp-1000000000-1100 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x03 0x0001>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1200000000,1000 {
opp-1200000000-1000 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x08 0x0004>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1050 {
opp-1200000000-1050 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x04 0x0004>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1100 {
opp-1200000000-1100 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x02 0x0004>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1125 {
opp-1200000000-1125 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x01 0x0004>;
opp-hz = /bits/ 64 <1200000000>;

21
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -339,7 +339,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -565,6 +565,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
@ -595,8 +596,6 @@ usb-phy@c5000000 {
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
@ -640,7 +639,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -666,7 +665,7 @@ panel: panel {
backlight = <&backlight>;
};
vdd_5v0_reg: regulator@0 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@ -674,7 +673,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
regulator@1 {
regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@ -682,7 +681,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@ -691,7 +690,7 @@ regulator@2 {
enable-active-high;
};
pci_vdd_reg: regulator@3 {
pci_vdd_reg: regulator-1v05 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;
@ -700,7 +699,7 @@ pci_vdd_reg: regulator@3 {
enable-active-high;
};
vdd_pnl_reg: regulator@4 {
vdd_pnl_reg: regulator-pn1 {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@ -709,7 +708,7 @@ vdd_pnl_reg: regulator@4 {
enable-active-high;
};
vdd_bl_reg: regulator@5 {
vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
@ -718,7 +717,7 @@ vdd_bl_reg: regulator@5 {
enable-active-high;
};
vdd_5v0_hdmi: regulator@6 {
vdd_5v0_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDDIO_HDMI";
regulator-min-microvolt = <5000000>;

11
arch/arm/boot/dts/tegra20-medcom-wide.dts
View File

@ -54,6 +54,9 @@ backlight: backlight {
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
/* close enough */
power-supply = <&vdd_3v3_reg>;
};
panel: panel {
@ -92,7 +95,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
vcc_24v_reg: regulator@100 {
vcc_24v_reg: regulator-24v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@ -100,7 +103,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
vdd_5v0_reg: regulator@101 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@ -109,7 +112,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
vdd_3v3_reg: regulator@102 {
vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@ -118,7 +121,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
vdd_1v8_reg: regulator@103 {
vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;

22
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -264,8 +264,16 @@ conf_ld17_0 {
};
};
spdif@70002400 {
status = "okay";
nvidia,fixed-parent-rate;
};
i2s@70002800 {
status = "okay";
nvidia,fixed-parent-rate;
};
serial@70006000 {
@ -519,6 +527,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <0>;
nvidia,sys-clock-req-active-high;
core-supply = <&core_vdd_reg>;
};
usb@c5000000 {
@ -533,8 +542,6 @@ usb-phy@c5000000 {
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
@ -573,9 +580,12 @@ backlight: backlight {
brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
default-brightness-level = <10>;
/* close enough */
power-supply = <&vdd_pnl_reg>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -612,7 +622,7 @@ panel: panel {
backlight = <&backlight>;
};
p5valw_reg: regulator@0 {
p5valw_reg: regulator-5v0alw {
compatible = "regulator-fixed";
regulator-name = "+5valw";
regulator-min-microvolt = <5000000>;
@ -620,7 +630,7 @@ p5valw_reg: regulator@0 {
regulator-always-on;
};
vdd_pnl_reg: regulator@1 {
vdd_pnl_reg: regulator-3v0 {
compatible = "regulator-fixed";
regulator-name = "+3VS,vdd_pnl";
regulator-min-microvolt = <3300000>;
@ -705,5 +715,5 @@ map0 {
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@760000000;
/delete-node/ opp-760000000;
};

948
arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
View File

File diff suppressed because it is too large Load Diff

8
arch/arm/boot/dts/tegra20-plutux.dts
View File

@ -60,7 +60,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
vcc_24v_reg: regulator@100 {
vcc_24v_reg: regulator-24v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@ -68,7 +68,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
vdd_5v0_reg: regulator@101 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@ -77,7 +77,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
vdd_3v3_reg: regulator@102 {
vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@ -86,7 +86,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
vdd_1v8_reg: regulator@103 {
vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;

23
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@ -358,7 +358,7 @@ isl29018@44 {
};
gyrometer@68 {
compatible = "invn,mpu3050";
compatible = "invensense,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
@ -444,7 +444,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
@ -689,6 +689,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
memory-controller@7000f400 {
@ -742,8 +743,6 @@ usb-phy@c5000000 {
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
@ -792,7 +791,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -828,7 +827,7 @@ panel: panel {
ddc-i2c-bus = <&lvds_ddc>;
};
vdd_5v0_reg: regulator@0 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@ -836,7 +835,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
regulator@1 {
regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@ -844,7 +843,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@ -853,7 +852,7 @@ regulator@2 {
enable-active-high;
};
vbus_reg: regulator@3 {
vbus_reg: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "vdd_vbus_wup1";
regulator-min-microvolt = <5000000>;
@ -864,7 +863,7 @@ vbus_reg: regulator@3 {
regulator-boot-on;
};
vdd_pnl_reg: regulator@4 {
vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@ -873,7 +872,7 @@ vdd_pnl_reg: regulator@4 {
enable-active-high;
};
vdd_bl_reg: regulator@5 {
vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
@ -882,7 +881,7 @@ vdd_bl_reg: regulator@5 {
enable-active-high;
};
vdd_hdmi: regulator@6 {
vdd_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDDIO_HDMI";
regulator-min-microvolt = <5000000>;

7
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -357,7 +357,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sys_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -477,6 +477,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
@ -502,13 +503,13 @@ mmc@c8000600 {
status = "okay";
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
pci_vdd_reg: regulator@1 {
pci_vdd_reg: regulator-1v05 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;

8
arch/arm/boot/dts/tegra20-tec.dts
View File

@ -69,7 +69,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
vcc_24v_reg: regulator@100 {
vcc_24v_reg: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@ -77,7 +77,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
vdd_5v0_reg: regulator@101 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@ -86,7 +86,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
vdd_3v3_reg: regulator@102 {
vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@ -95,7 +95,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
vdd_1v8_reg: regulator@103 {
vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;

26
arch/arm/boot/dts/tegra20-trimslice.dts
View File

@ -287,7 +287,8 @@ dvi_ddc: i2c@7000c000 {
spi@7000c380 {
status = "okay";
spi-max-frequency = <48000000>;
spi-flash@0 {
flash@0 {
compatible = "winbond,w25q80bl", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <48000000>;
@ -321,6 +322,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
@ -348,8 +350,6 @@ usb-phy@c5000000 {
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
@ -379,7 +379,7 @@ mmc@c8000600 {
bus-width = <4>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -401,7 +401,7 @@ poweroff {
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
hdmi_vdd_reg: regulator@0 {
hdmi_vdd_reg: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "avdd_hdmi";
regulator-min-microvolt = <3300000>;
@ -409,7 +409,7 @@ hdmi_vdd_reg: regulator@0 {
regulator-always-on;
};
hdmi_pll_reg: regulator@1 {
hdmi_pll_reg: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
@ -417,7 +417,7 @@ hdmi_pll_reg: regulator@1 {
regulator-always-on;
};
vbus_reg: regulator@2 {
vbus_reg: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@ -428,7 +428,7 @@ vbus_reg: regulator@2 {
regulator-boot-on;
};
pci_clk_reg: regulator@3 {
pci_clk_reg: regulator-pciclk {
compatible = "regulator-fixed";
regulator-name = "pci_clk";
regulator-min-microvolt = <3300000>;
@ -436,7 +436,7 @@ pci_clk_reg: regulator@3 {
regulator-always-on;
};
pci_vdd_reg: regulator@4 {
pci_vdd_reg: regulator-pcivdd {
compatible = "regulator-fixed";
regulator-name = "pci_vdd";
regulator-min-microvolt = <1050000>;
@ -444,6 +444,14 @@ pci_vdd_reg: regulator@4 {
regulator-always-on;
};
vdd_core: regulator-core {
compatible = "regulator-fixed";
regulator-name = "vdd_core";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;

15
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -544,6 +544,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
usb@c5000000 {
@ -556,8 +557,6 @@ usb-phy@c5000000 {
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
@ -606,7 +605,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -647,7 +646,7 @@ panel: panel {
ddc-i2c-bus = <&lvds_ddc>;
};
vdd_5v0_reg: regulator@0 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@ -655,7 +654,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
regulator@1 {
regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@ -663,7 +662,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@ -672,7 +671,7 @@ regulator@2 {
enable-active-high;
};
vdd_pnl_reg: regulator@3 {
vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@ -681,7 +680,7 @@ vdd_pnl_reg: regulator@3 {
enable-active-high;
};
vdd_bl_reg: regulator@4 {
vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;

162
arch/arm/boot/dts/tegra20.dtsi
View File

@ -40,8 +40,10 @@ host1x@50000000 {
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
reset-names = "host1x", "mc";
power-domains = <&pd_core>;
operating-points-v2 = <&host1x_dvfs_opp_table>;
#address-cells = <1>;
#size-cells = <1>;
@ -55,6 +57,9 @@ mpe@54040000 {
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
power-domains = <&pd_mpe>;
operating-points-v2 = <&mpe_dvfs_opp_table>;
status = "disabled";
};
vi@54080000 {
@ -64,6 +69,9 @@ vi@54080000 {
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
power-domains = <&pd_venc>;
operating-points-v2 = <&vi_dvfs_opp_table>;
status = "disabled";
};
epp@540c0000 {
@ -73,6 +81,9 @@ epp@540c0000 {
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
power-domains = <&pd_core>;
operating-points-v2 = <&epp_dvfs_opp_table>;
status = "disabled";
};
isp@54100000 {
@ -82,6 +93,8 @@ isp@54100000 {
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
power-domains = <&pd_venc>;
status = "disabled";
};
gr2d@54140000 {
@ -89,16 +102,20 @@ gr2d@54140000 {
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
reset-names = "2d", "mc";
power-domains = <&pd_core>;
operating-points-v2 = <&gr2d_dvfs_opp_table>;
};
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
reset-names = "3d", "mc";
power-domains = <&pd_3d>;
operating-points-v2 = <&gr3d_dvfs_opp_table>;
};
dc@54200000 {
@ -110,6 +127,8 @@ dc@54200000 {
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp1_dvfs_opp_table>;
nvidia,head = <0>;
@ -138,6 +157,8 @@ dc@54240000 {
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp2_dvfs_opp_table>;
nvidia,head = <1>;
@ -157,7 +178,7 @@ rgb {
};
};
hdmi@54280000 {
tegra_hdmi: hdmi@54280000 {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@ -166,6 +187,9 @@ hdmi@54280000 {
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
power-domains = <&pd_core>;
operating-points-v2 = <&hdmi_dvfs_opp_table>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -174,6 +198,8 @@ tvo@542c0000 {
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
power-domains = <&pd_core>;
operating-points-v2 = <&tvo_dvfs_opp_table>;
status = "disabled";
};
@ -185,6 +211,8 @@ dsi@54300000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsi_dvfs_opp_table>;
status = "disabled";
};
};
@ -242,6 +270,13 @@ tegra_car: clock@60006000 {
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
sclk {
compatible = "nvidia,tegra20-sclk";
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
power-domains = <&pd_core>;
operating-points-v2 = <&sclk_dvfs_opp_table>;
};
};
flow-controller@60007000 {
@ -293,9 +328,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 224>;
*/
};
vde@6001a000 {
@ -319,6 +352,8 @@ vde@6001a000 {
clocks = <&tegra_car TEGRA20_CLK_VDE>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
power-domains = <&pd_vde>;
operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
@ -352,6 +387,23 @@ tegra_ac97: ac97@70002000 {
status = "disabled";
};
tegra_spdif: spdif@70002400 {
compatible = "nvidia,tegra20-spdif";
reg = <0x70002400 0x200>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>,
<&tegra_car TEGRA20_CLK_SPDIF_IN>;
clock-names = "out", "in";
resets = <&tegra_car 10>;
dmas = <&apbdma 3>, <&apbdma 3>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
status = "disabled";
assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>;
assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
};
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
@ -460,6 +512,8 @@ nand-controller@70008000 {
reset-names = "nand";
assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
assigned-clock-rates = <150000000>;
power-domains = <&pd_core>;
operating-points-v2 = <&ndflash_dvfs_opp_table>;
status = "disabled";
};
@ -473,6 +527,8 @@ gmi@70009000 {
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
power-domains = <&pd_core>;
operating-points-v2 = <&nor_dvfs_opp_table>;
status = "disabled";
};
@ -523,7 +579,7 @@ spi@7000c380 {
status = "disabled";
};
i2c@7000c400 {
i2c2: i2c@7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@ -643,6 +699,52 @@ tegra_pmc: pmc@7000e400 {
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
pd_core: core-domain {
#power-domain-cells = <0>;
operating-points-v2 = <&core_opp_table>;
};
powergates {
pd_3d: td {
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&mc TEGRA20_MC_RESET_3D>,
<&tegra_car TEGRA20_CLK_GR3D>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_venc: venc {
clocks = <&tegra_car TEGRA20_CLK_ISP>,
<&tegra_car TEGRA20_CLK_VI>,
<&tegra_car TEGRA20_CLK_CSI>;
resets = <&mc TEGRA20_MC_RESET_ISP>,
<&mc TEGRA20_MC_RESET_VI>,
<&tegra_car TEGRA20_CLK_ISP>,
<&tegra_car 20 /* VI */>,
<&tegra_car TEGRA20_CLK_CSI>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_vde: vdec {
clocks = <&tegra_car TEGRA20_CLK_VDE>;
resets = <&mc TEGRA20_MC_RESET_VDE>,
<&tegra_car TEGRA20_CLK_VDE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_mpe: mpe {
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&mc TEGRA20_MC_RESET_MPEA>,
<&mc TEGRA20_MC_RESET_MPEB>,
<&mc TEGRA20_MC_RESET_MPEC>,
<&tegra_car TEGRA20_CLK_MPE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};
mc: memory-controller@7000f000 {
@ -662,12 +764,13 @@ emc: memory-controller@7000f400 {
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
power-domains = <&pd_core>;
#address-cells = <1>;
#size-cells = <0>;
#interconnect-cells = <0>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
};
fuse@7000f800 {
@ -712,6 +815,9 @@ pcie@80003000 {
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
power-domains = <&pd_core>;
operating-points-v2 = <&pcie_dvfs_opp_table>;
status = "disabled";
pci@1,0 {
@ -753,6 +859,8 @@ usb@c5000000 {
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
power-domains = <&pd_core>;
operating-points-v2 = <&usbd_dvfs_opp_table>;
status = "disabled";
};
@ -792,6 +900,8 @@ usb@c5004000 {
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb2_dvfs_opp_table>;
status = "disabled";
};
@ -820,6 +930,8 @@ usb@c5008000 {
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb3_dvfs_opp_table>;
status = "disabled";
};
@ -856,6 +968,8 @@ mmc@c8000000 {
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
status = "disabled";
};
@ -867,6 +981,8 @@ mmc@c8000200 {
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
status = "disabled";
};
@ -878,6 +994,8 @@ mmc@c8000400 {
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
status = "disabled";
};
@ -889,6 +1007,8 @@ mmc@c8000600 {
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
status = "disabled";
};
@ -918,4 +1038,24 @@ pmu {
interrupt-affinity = <&{/cpus/cpu@0}>,
<&{/cpus/cpu@1}>;
};
sound-hdmi {
compatible = "simple-audio-card";
simple-audio-card,name = "NVIDIA Tegra20 HDMI";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
cpu {
sound-dai = <&tegra_spdif>;
};
codec {
sound-dai = <&tegra_hdmi>;
};
};
};
};

2
arch/arm/boot/dts/tegra30-apalis-eval.dts
View File

@ -239,7 +239,7 @@ reg_usbh_vbus: regulator-usbh-vbus {
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
pex-perst-n {
pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
output-high;

2
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
View File

@ -257,7 +257,7 @@ reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
pex-perst-n {
pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
output-high;

6
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
View File

@ -829,14 +829,17 @@ pv0 {
serial@70006040 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
hdmi_ddc: i2c@7000c700 {
@ -1047,9 +1050,6 @@ regulator@60 {
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-low;
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
ti,vsel1-state-low;
};
};

6
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -820,14 +820,17 @@ pv0 {
serial@70006040 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
hdmi_ddc: i2c@7000c700 {
@ -1030,9 +1033,6 @@ regulator@60 {
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-low;
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
ti,vsel1-state-low;
};
};

61
arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi Normal file
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0
/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */
/ {
host1x@50000000 {
lcd: dc@54200000 {
rgb {
status = "okay";
port@0 {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
display-panel {
power-supply = <&vdd_pnl>;
ddc-i2c-bus = <&lcd_ddc>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
/* Texas Instruments SN75LVDS83B LVDS Transmitter */
lvds-encoder {
compatible = "ti,sn75lvds83", "lvds-encoder";
powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
power-supply = <&vdd_3v3_sys>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};

67
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
View File

@ -8,6 +8,7 @@
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
#include "tegra30-asus-lvds-display.dtsi"
/ {
aliases {
@ -59,21 +60,6 @@ trustzone@bfe00000 {
};
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
port@0 {
lcd_output: endpoint {
remote-endpoint = <&lvds_encoder_input>;
bus-width = <24>;
};
};
};
};
};
gpio@6000d000 {
init-mode-hog {
gpio-hog;
@ -804,11 +790,13 @@ drive_gma {
uartb: serial@70006040 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
/* GPS BCM4751 */
};
uartc: serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
status = "okay";
nvidia,adjust-baud-rates = <0 9600 100>,
@ -980,6 +968,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
ahub@70080000 {
@ -1069,7 +1058,7 @@ battery_cell: battery-cell {
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@ -1114,20 +1103,14 @@ display-panel {
*/
compatible = "panel-lvds";
power-supply = <&vdd_pnl>;
backlight = <&backlight>;
width-mm = <94>;
height-mm = <150>;
rotation = <180>;
data-mapping = "jeida-24";
port {
panel_input: endpoint {
remote-endpoint = <&lvds_encoder_output>;
};
};
/* DDC unconnected on Nexus 7 */
/delete-property/ ddc-i2c-bus;
};
firmware {
@ -1179,35 +1162,7 @@ volume-down {
};
};
lvds-encoder {
compatible = "ti,sn75lvds83", "lvds-encoder";
powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
power-supply = <&vdd_3v3_sys>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_encoder_input: endpoint {
remote-endpoint = <&lcd_output>;
};
};
port@1 {
reg = <1>;
lvds_encoder_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
vdd_5v0_sys: regulator@0 {
vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@ -1216,7 +1171,7 @@ vdd_5v0_sys: regulator@0 {
regulator-boot-on;
};
vdd_3v3_sys: regulator@1 {
vdd_3v3_sys: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
@ -1226,7 +1181,7 @@ vdd_3v3_sys: regulator@1 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_pnl: regulator@2 {
vdd_pnl: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
@ -1237,7 +1192,7 @@ vdd_pnl: regulator@2 {
vin-supply = <&vdd_3v3_sys>;
};
vcc_3v3_ts: regulator@3 {
vcc_3v3_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "ldo_s-1167_3v3";
regulator-min-microvolt = <3300000>;

4
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
View File

@ -166,12 +166,12 @@ ldo8 {
};
};
vdd_3v3_sys: regulator@1 {
vdd_3v3_sys: regulator-3v3 {
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
regulator@4 {
regulator-usb {
compatible = "regulator-fixed";
regulator-name = "avdd_usb";
regulator-min-microvolt = <3300000>;

12
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
View File

@ -1565,13 +1565,13 @@ timing-667000000 {
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp@750000000,1300;
/delete-node/ opp@800000000,1300;
/delete-node/ opp@900000000,1350;
/delete-node/ opp-750000000-1300;
/delete-node/ opp-800000000-1300;
/delete-node/ opp-900000000-1350;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp@750000000;
/delete-node/ opp@800000000;
/delete-node/ opp@900000000;
/delete-node/ opp-750000000;
/delete-node/ opp-800000000;
/delete-node/ opp-900000000;
};

2
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
View File

@ -143,7 +143,7 @@ vdd_core: core-regulator@60 {
};
};
vdd_3v3_sys: regulator@1 {
vdd_3v3_sys: regulator-3v3 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

1
arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
View File

@ -137,7 +137,6 @@ i2c@7000c500 {
nfc@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
clock-frequency = <100000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;

2
arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
View File

@ -223,8 +223,6 @@ nfc@2a {
compatible = "nxp,pn544-i2c";
reg = <0x2a>;
clock-frequency = <100000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;

627
arch/arm/boot/dts/tegra30-asus-tf201.dts Normal file
View File

@ -0,0 +1,627 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer-common.dtsi"
#include "tegra30-asus-lvds-display.dtsi"
/ {
model = "Asus Transformer Prime TF201";
compatible = "asus,tf201", "nvidia,tegra30";
pinmux@70000868 {
state_default: pinmux {
lcd_pwr2_pc6 {
nvidia,pins = "lcd_pwr2_pc6",
"lcd_dc1_pd2";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pbb3 {
nvidia,pins = "pbb3";
nvidia,function = "vgp3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pbb7 {
nvidia,pins = "pbb7";
nvidia,function = "i2s4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
gmi_cs4_n_pk2 {
nvidia,pins = "gmi_cs4_n_pk2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
serial@70006200 {
/* Azurewave AW-NH615 BCM4329B1 */
bluetooth {
compatible = "brcm,bcm4329-bt";
};
};
i2c@7000c400 {
/* Atmel MXT768E touchscreen */
touchscreen@4d {
compatible = "atmel,maxtouch";
reg = <0x4d>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
vdda-supply = <&vdd_3v3_sys>;
vdd-supply = <&vdd_3v3_sys>;
};
};
i2c@7000c500 {
clock-frequency = <100000>;
magnetometer@e {
mount-matrix = "-1", "0", "0",
"0", "-1", "0",
"0", "0", "-1";
};
gyroscope@68 {
mount-matrix = "0", "-1", "0",
"-1", "0", "0",
"0", "0", "-1";
/* External I2C interface */
i2c-gate {
accelerometer@f {
mount-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "1";
};
};
};
};
i2c@7000d000 {
/* Realtek ALC5631 audio codec */
rt5631: audio-codec@1a {
compatible = "realtek,rt5631";
reg = <0x1a>;
};
};
memory-controller@7000f000 {
emc-timings-0 {
/* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
nvidia,ram-code = <0>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00020001 0x80000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x73e30303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010001 0x80000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x72c30303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000001 0x80000018
0x00000001 0x00000001 0x00000003 0x00000001
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060403 0x72430504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000003 0x80000025
0x00000001 0x00000001 0x00000006 0x00000003
0x00000005 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000003 0x00000002
0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emem-configuration = < 0x00000006 0x80000048
0x00000002 0x00000003 0x0000000c 0x00000007
0x00000009 0x00000001 0x00000002 0x00000006
0x00000001 0x00000000 0x00000004 0x00000004
0x04040001 0x000d090c 0x71c6120d 0x001f0000 >;
};
};
emc-timings-1 {
/* TF201 Unknown 1GB LPDDR2 500MHZ */
nvidia,ram-code = <1>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00020001 0x80000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x73e30303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010001 0x80000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x72c30303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000001 0x80000018
0x00000001 0x00000001 0x00000003 0x00000001
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060403 0x72430504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000003 0x80000025
0x00000001 0x00000001 0x00000006 0x00000003
0x00000005 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000003 0x00000002
0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
};
timing-500000000 {
clock-frequency = <500000000>;
nvidia,emem-configuration = < 0x00000007 0x8000005a
0x00000003 0x00000004 0x0000000e 0x00000009
0x0000000c 0x00000002 0x00000002 0x00000008
0x00000001 0x00000000 0x00000004 0x00000005
0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >;
};
};
};
memory-controller@7000f400 {
emc-timings-0 {
/* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
nvidia,ram-code = <0>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000003 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x0000000a 0x00000060 0x00000000 0x00000018
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000004 0x00000004
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x0000006b 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x00098000 0x00098000 0x00098000
0x00098000 0x00000010 0x00000010 0x00000010
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000008 0x00000008 0x00000008
0x00000008 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00000000
0x00000009 0x00090009 0xa0f10000 0x00000000
0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000003
0x00000006 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x0000000a 0x000000c0 0x00000000 0x00000030
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000008 0x00000008
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000000d5 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x00098000 0x00098000 0x00098000
0x00098000 0x00000010 0x00000010 0x00000010
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000018 0x00000018 0x00000018
0x00000018 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00000000
0x00000009 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x0000000a>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000006
0x0000000d 0x00000004 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x0000000a 0x00000181 0x00000000 0x00000060
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x0000000f 0x0000000f
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000001a9 0x00000004 0x00000006
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x000a0000 0x000a0000 0x000a0000
0x000a0000 0x00000010 0x00000010 0x00000010
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000008 0x00000008 0x00000008
0x00000008 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x00120220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00000000
0x0000000a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000013>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000c
0x0000001a 0x00000008 0x00000003 0x00000005
0x00000004 0x00000001 0x00000006 0x00000003
0x00000003 0x00000002 0x00000002 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000c
0x0000000a 0x00000303 0x00000000 0x000000c0
0x00000001 0x00000001 0x00000003 0x00000000
0x00000001 0x00000007 0x0000001d 0x0000001d
0x00000004 0x0000000b 0x00000005 0x00000004
0x00000002 0x00000351 0x00000004 0x00000006
0x00000000 0x00000000 0x00004282 0x00440084
0x00008000 0x00074000 0x00074000 0x00074000
0x00074000 0x00000010 0x00000010 0x00000010
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000018 0x00000018 0x00000018
0x00000018 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00078000 0x00078000 0x00078000
0x00078000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00000000
0x00000013 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010082>;
nvidia,emc-mode-2 = <0x00020004>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000024>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000017
0x00000033 0x00000010 0x00000007 0x00000007
0x00000007 0x00000002 0x0000000a 0x00000007
0x00000007 0x00000003 0x00000002 0x00000000
0x00000003 0x00000007 0x00000004 0x0000000d
0x0000000e 0x000005e9 0x00000000 0x0000017a
0x00000002 0x00000002 0x00000007 0x00000000
0x00000001 0x0000000c 0x00000038 0x00000038
0x00000006 0x00000014 0x00000009 0x00000004
0x00000002 0x00000680 0x00000000 0x00000006
0x00000000 0x00000000 0x00006282 0x001d0084
0x00008000 0x0002c000 0x0002c000 0x0002c000
0x0002c000 0x00000010 0x00000010 0x00000010
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000008 0x00000008 0x00000008
0x00000008 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00048000 0x00048000 0x00048000
0x00048000 0x000c0220 0x0800003d 0x00000000
0x77ffc004 0x01f1f408 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00000000
0x00000024 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
};
};
emc-timings-1 {
/* TF201 Unknown 1GB LPDDR2 500MHZ */
nvidia,ram-code = <1>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000003 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000060 0x00000000 0x00000018
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000004 0x00000004
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x0000006b 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000000a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000003
0x00000006 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x000000c0 0x00000000 0x00000030
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000008 0x00000008
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000000d5 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000013 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x0000000a>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000006
0x0000000d 0x00000004 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000181 0x00000000 0x00000060
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x0000000f 0x0000000f
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000001a9 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x00780084
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000025 0x00090009 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000013>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000c
0x0000001a 0x00000008 0x00000003 0x00000005
0x00000004 0x00000001 0x00000006 0x00000003
0x00000003 0x00000002 0x00000002 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000c
0x0000000a 0x00000303 0x00000000 0x000000c0
0x00000001 0x00000001 0x00000003 0x00000000
0x00000001 0x00000007 0x0000001d 0x0000001d
0x00000004 0x0000000b 0x00000005 0x00000004
0x00000002 0x00000351 0x00000004 0x00000006
0x00000000 0x00000000 0x00004282 0x00440084
0x00008000 0x00060000 0x00060000 0x00060000
0x00060000 0x00072000 0x00072000 0x00072000
0x00072000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000d0000 0x000d0000 0x000d0000
0x000d0000 0x000e0220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000004a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
};
timing-500000000 {
clock-frequency = <500000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x000100c2>;
nvidia,emc-mode-2 = <0x00020005>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x0000002d>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000001d
0x00000040 0x00000014 0x00000008 0x00000007
0x00000009 0x00000003 0x0000000d 0x00000008
0x00000008 0x00000004 0x00000002 0x00000000
0x00000004 0x00000008 0x00000005 0x0000000d
0x0000000f 0x00000763 0x00000000 0x000001d8
0x00000003 0x00000003 0x00000008 0x00000000
0x00000001 0x0000000e 0x00000046 0x00000046
0x00000008 0x00000019 0x0000000b 0x00000004
0x00000002 0x00000820 0x00000000 0x00000006
0x00000000 0x00000000 0x00006282 0xf0140091
0x00008000 0x00000008 0x00000008 0x00000008
0x00000008 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x0000000c 0x0000000c 0x0000000c
0x0000000c 0x00080220 0x0800003d 0x00000000
0x77ffc004 0x01f1f408 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x000000b4 0x000d000d 0xa0f10404 0x00000000
0x00000000 0x80000fde 0xe0000000 0xff00ff88 >;
};
};
};
usb-phy@7d000000 {
/delete-property/ nvidia,xcvr-setup-use-fuses;
nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
};
usb-phy@7d008000 {
/delete-property/ nvidia,xcvr-setup-use-fuses;
nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
};
display-panel {
compatible = "hannstar,hsd101pww2";
};
haptic-feedback {
compatible = "gpio-vibrator";
enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
vcc-supply = <&vdd_3v3_sys>;
};
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp-533000000-1200;
/delete-node/ opp-625000000-1200;
/delete-node/ opp-625000000-1250;
/delete-node/ opp-667000000-1200;
/delete-node/ opp-750000000-1300;
/delete-node/ opp-800000000-1300;
/delete-node/ opp-900000000-1350;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp-533000000;
/delete-node/ opp-625000000;
/delete-node/ opp-667000000;
/delete-node/ opp-750000000;
/delete-node/ opp-800000000;
/delete-node/ opp-900000000;
};

1034
arch/arm/boot/dts/tegra30-asus-tf300t.dts Normal file
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1087
arch/arm/boot/dts/tegra30-asus-tf300tg.dts Normal file
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arch/arm/boot/dts/tegra30-asus-tf700t.dts Normal file
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@ -0,0 +1,823 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer-common.dtsi"
/ {
model = "Asus Transformer Infinity TF700T";
compatible = "asus,tf700t", "nvidia,tegra30";
host1x@50000000 {
lcd: dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
rgb {
status = "okay";
port@0 {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
pinmux@70000868 {
state_default: pinmux {
lcd_pwr2_pc6 {
nvidia,pins = "lcd_pwr2_pc6",
"lcd_dc1_pd2";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pbb3 {
nvidia,pins = "pbb3";
nvidia,function = "vgp3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
spi2_mosi_px0 {
nvidia,pins = "spi2_mosi_px0";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pbb7 {
nvidia,pins = "pbb7";
nvidia,function = "i2s4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gmi_cs4_n_pk2 {
nvidia,pins = "gmi_cs4_n_pk2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
serial@70006200 {
/* Azurewave AW-NH665 BCM4330B1 */
bluetooth {
compatible = "brcm,bcm4330-bt";
};
};
i2c@7000c400 {
/* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */
touchscreen@10 {
compatible = "elan,ektf3624";
reg = <0x10>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
vcc33-supply = <&vdd_3v3_sys>;
vccio-supply = <&vdd_3v3_sys>;
touchscreen-size-x = <2944>;
touchscreen-size-y = <1856>;
touchscreen-inverted-y;
};
};
i2c@7000c500 {
clock-frequency = <100000>;
magnetometer@e {
mount-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "-1";
};
gyroscope@68 {
mount-matrix = "0", "1", "0",
"1", "0", "0",
"0", "0", "-1";
/* External I2C interface */
i2c-gate {
accelerometer@f {
mount-matrix = "0", "-1", "0",
"-1", "0", "0",
"0", "0", "1";
};
};
};
};
i2c@7000d000 {
/* Realtek ALC5631 audio codec */
rt5631: audio-codec@1a {
compatible = "realtek,rt5631";
reg = <0x1a>;
};
};
memory-controller@7000f000 {
emc-timings-0 {
/* Micron 1GB 800MHZ */
nvidia,ram-code = <0>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00020001 0xc0000020
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0502 0x75830303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010001 0xc0000020
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0502 0x74630303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000001 0xc0000030
0x00000001 0x00000001 0x00000003 0x00000000
0x00000002 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000003 0xc0000025
0x00000001 0x00000001 0x00000005 0x00000002
0x00000004 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emem-configuration = < 0x00000006 0xc0000048
0x00000001 0x00000002 0x00000009 0x00000005
0x00000007 0x00000001 0x00000002 0x00000008
0x00000002 0x00000002 0x00000003 0x00000006
0x06030202 0x000d0709 0x7086120a 0x001f0000 >;
};
timing-800000000 {
clock-frequency = <800000000>;
nvidia,emem-configuration = < 0x0000000c 0xc0000090
0x00000004 0x00000005 0x00000013 0x0000000c
0x0000000f 0x00000002 0x00000003 0x0000000c
0x00000002 0x00000002 0x00000004 0x00000008
0x08040202 0x00160d13 0x712c2414 0x001f0000 >;
};
};
emc-timings-1 {
/* Elpida 1GB 800MHZ */
nvidia,ram-code = <1>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00020001 0xc0000020
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0502 0x75830303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010001 0xc0000020
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0502 0x74630303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000001 0xc0000030
0x00000001 0x00000001 0x00000003 0x00000000
0x00000002 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000003 0xc0000025
0x00000001 0x00000001 0x00000005 0x00000002
0x00000004 0x00000001 0x00000003 0x00000008
0x00000002 0x00000001 0x00000002 0x00000006
0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emem-configuration = < 0x00000006 0xc0000048
0x00000001 0x00000002 0x00000009 0x00000005
0x00000007 0x00000001 0x00000002 0x00000008
0x00000002 0x00000002 0x00000003 0x00000006
0x06030202 0x000d0709 0x7086120a 0x001f0000 >;
};
timing-800000000 {
clock-frequency = <800000000>;
nvidia,emem-configuration = < 0x0000000c 0xc0000090
0x00000004 0x00000005 0x00000013 0x0000000c
0x0000000f 0x00000002 0x00000003 0x0000000c
0x00000002 0x00000002 0x00000004 0x00000008
0x08040202 0x00160d13 0x712c2414 0x001f0000 >;
};
};
};
memory-controller@7000f400 {
emc-timings-0 {
/* Micron 1GB 800MHZ */
nvidia,ram-code = <0>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000006 0x00000000 0x00000000 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000000
0x00000000 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x000000c0 0x00000000 0x00000030
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x00000007 0x00000007
0x00000004 0x00000002 0x00000000 0x00000004
0x00000005 0x000000c7 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000002
0x0000000d 0x00000001 0x00000000 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000000
0x00000000 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x00000181 0x00000000 0x00000060
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x0000000e 0x0000000e
0x00000004 0x00000003 0x00000000 0x00000004
0x00000005 0x0000018e 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000004
0x0000001a 0x00000003 0x00000001 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000001
0x00000001 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x00000303 0x00000000 0x000000c0
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x0000001c 0x0000001c
0x00000004 0x00000005 0x00000000 0x00000004
0x00000005 0x0000031c 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000009
0x00000035 0x00000007 0x00000002 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000002
0x00000002 0x00000003 0x00000001 0x00000000
0x00000005 0x00000006 0x00000004 0x0000000a
0x0000000b 0x00000607 0x00000000 0x00000181
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x00000038 0x00000038
0x00000004 0x00000009 0x00000000 0x00000004
0x00000005 0x00000638 0x00000007 0x00000004
0x00000000 0x00000000 0x00004288 0x004400a4
0x00008000 0x00080000 0x00080000 0x00080000
0x00080000 0x00080000 0x00080000 0x00080000
0x00080000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00020000
0x00000100 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200000>;
nvidia,emc-mode-reset = <0x80000521>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-configuration = < 0x00000012
0x00000066 0x0000000c 0x00000004 0x00000003
0x00000008 0x00000002 0x0000000a 0x00000004
0x00000004 0x00000002 0x00000001 0x00000000
0x00000004 0x00000006 0x00000004 0x0000000a
0x0000000c 0x00000bf0 0x00000000 0x000002fc
0x00000001 0x00000008 0x00000001 0x00000000
0x00000008 0x0000000f 0x0000006c 0x00000200
0x00000004 0x00000010 0x00000000 0x00000004
0x00000005 0x00000c30 0x00000000 0x00000004
0x00000000 0x00000000 0x00007088 0x001d0084
0x00008000 0x00044000 0x00044000 0x00044000
0x00044000 0x00014000 0x00014000 0x00014000
0x00014000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00048000 0x00048000 0x00048000
0x00048000 0x000002a0 0x0600013d 0x00000000
0x77fff884 0x01f1f508 0x05057404 0x54000007
0x080001e8 0x08000021 0x00000802 0x00020000
0x00000100 0x0158000c 0xa0f10000 0x00000000
0x00000000 0x800018c8 0xe8000000 0xff00ff89 >;
};
timing-800000000 {
clock-frequency = <800000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000d71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000025
0x000000ce 0x0000001a 0x00000009 0x00000005
0x0000000d 0x00000004 0x00000013 0x00000009
0x00000009 0x00000004 0x00000001 0x00000000
0x00000007 0x0000000a 0x00000009 0x0000000a
0x00000011 0x00001820 0x00000000 0x00000608
0x00000003 0x00000012 0x00000001 0x00000000
0x0000000f 0x00000018 0x000000d8 0x00000200
0x00000005 0x00000020 0x00000000 0x00000007
0x00000008 0x00001860 0x0000000b 0x00000006
0x00000000 0x00000000 0x00005088 0xf0070191
0x00008000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00018000 0x00018000 0x00018000
0x00018000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x000002a0 0x0800013d 0x22220000
0x77fff884 0x01f1f501 0x07077404 0x54000000
0x080001e8 0x08000021 0x00000802 0x00020000
0x00000100 0x00f0000c 0xa0f10000 0x00000000
0x00000000 0x8000308c 0xe8000000 0xff00ff49 >;
};
};
emc-timings-1 {
/* Elpida 1GB 800MHZ */
nvidia,ram-code = <1>;
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000006 0x00000000 0x00000000 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000000
0x00000000 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x000000c0 0x00000000 0x00000030
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x00000007 0x00000007
0x00000004 0x00000002 0x00000000 0x00000004
0x00000005 0x000000c7 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000002
0x0000000d 0x00000001 0x00000000 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000000
0x00000000 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x00000181 0x00000000 0x00000060
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x0000000e 0x0000000e
0x00000004 0x00000003 0x00000000 0x00000004
0x00000005 0x0000018e 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000004
0x0000001a 0x00000003 0x00000001 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000001
0x00000001 0x00000003 0x00000001 0x00000000
0x00000005 0x00000005 0x00000004 0x0000000a
0x0000000b 0x00000303 0x00000000 0x000000c0
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x0000001c 0x0000001c
0x00000004 0x00000005 0x00000000 0x00000004
0x00000005 0x0000031c 0x00000006 0x00000004
0x00000000 0x00000000 0x00004288 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00000000
0x00000040 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000009
0x00000035 0x00000007 0x00000002 0x00000002
0x0000000a 0x00000005 0x0000000b 0x00000002
0x00000002 0x00000003 0x00000001 0x00000000
0x00000005 0x00000006 0x00000004 0x0000000a
0x0000000b 0x00000607 0x00000000 0x00000181
0x00000002 0x00000002 0x00000001 0x00000000
0x00000007 0x0000000f 0x00000038 0x00000038
0x00000004 0x00000009 0x00000000 0x00000004
0x00000005 0x00000638 0x00000007 0x00000004
0x00000000 0x00000000 0x00004288 0x004400a4
0x00008000 0x00080000 0x00080000 0x00080000
0x00080000 0x00080000 0x00080000 0x00080000
0x00080000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x000002a0 0x0800211c 0x00000000
0x77fff884 0x01f1f108 0x05057404 0x54000007
0x08000168 0x08000000 0x00000802 0x00020000
0x00000100 0x000c000c 0xa0f10000 0x00000000
0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
};
timing-400000000 {
clock-frequency = <400000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200000>;
nvidia,emc-mode-reset = <0x80000521>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-configuration = < 0x00000012
0x00000066 0x0000000c 0x00000004 0x00000003
0x00000008 0x00000002 0x0000000a 0x00000004
0x00000004 0x00000002 0x00000001 0x00000000
0x00000004 0x00000006 0x00000004 0x0000000a
0x0000000c 0x00000bf0 0x00000000 0x000002fc
0x00000001 0x00000008 0x00000001 0x00000000
0x00000008 0x0000000f 0x0000006c 0x00000200
0x00000004 0x00000010 0x00000000 0x00000004
0x00000005 0x00000c30 0x00000000 0x00000004
0x00000000 0x00000000 0x00007088 0x001d0084
0x00008000 0x00044000 0x00044000 0x00044000
0x00044000 0x00014000 0x00014000 0x00014000
0x00014000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00048000 0x00048000 0x00048000
0x00048000 0x000002a0 0x0600013d 0x00000000
0x77fff884 0x01f1f508 0x05057404 0x54000007
0x080001e8 0x08000021 0x00000802 0x00020000
0x00000100 0x0158000c 0xa0f10000 0x00000000
0x00000000 0x800018c8 0xe8000000 0xff00ff89 >;
};
timing-800000000 {
clock-frequency = <800000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000d71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000025
0x000000ce 0x0000001a 0x00000009 0x00000005
0x0000000d 0x00000004 0x00000013 0x00000009
0x00000009 0x00000004 0x00000001 0x00000000
0x00000007 0x0000000a 0x00000009 0x0000000a
0x00000011 0x00001820 0x00000000 0x00000608
0x00000003 0x00000012 0x00000001 0x00000000
0x0000000f 0x00000018 0x000000d8 0x00000200
0x00000005 0x00000020 0x00000000 0x00000007
0x00000008 0x00001860 0x0000000b 0x00000006
0x00000000 0x00000000 0x00005088 0xf0070191
0x00008000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00018000 0x00018000 0x00018000
0x00018000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x000002a0 0x0a00013d 0x22220000
0x77fff884 0x01f1f501 0x07077404 0x54000000
0x080001e8 0x08000021 0x00000802 0x00020000
0x00000100 0x00f0000c 0xa0f10000 0x00000000
0x00000000 0x8000308c 0xe8000000 0xff00ff49 >;
};
};
};
tc358768_refclk: clock-tc358768 {
compatible = "fixed-clock";
clock-frequency = <23100000>;
clock-accuracy = <100>;
#clock-cells = <0>;
};
tc358768_osc: clock-tc358768-osc-gate {
compatible = "gpio-gate-clock";
enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
clocks = <&tc358768_refclk>;
#clock-cells = <0>;
};
haptic-feedback {
compatible = "gpio-vibrator";
enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
vcc-supply = <&vdd_3v3_sys>;
};
i2c-mux {
compatible = "i2c-mux-gpio";
mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
i2c-parent = <&lcd_ddc>;
idle-state = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dsi-bridge@7 {
compatible = "toshiba,tc358768";
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tc358768_osc>;
clock-names = "refclk";
reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
vddc-supply = <&vdd_1v2_mipi>;
vddio-supply = <&vdd_1v8_vio>;
vddmipi-supply = <&vdd_1v2_mipi>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
data-lines = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
/*
* Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
* LCD SuperIPS+ Full HD panel.
*/
panel@1 {
compatible = "panasonic,vvx10f004b00";
reg = <1>;
power-supply = <&vdd_pnl>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
};
vdd_1v2_mipi: regulator-mipi {
compatible = "regulator-fixed";
regulator-name = "tc358768_1v2_vdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <10000>;
regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
};
&emc_icc_dvfs_opp_table {
/delete-node/ opp-900000000-1350;
};
&emc_bw_dfs_opp_table {
/delete-node/ opp-900000000;
};

1787
arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

24
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -1898,7 +1898,8 @@ core_vdd_reg: tps62361@60 {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@1 {
flash@1 {
compatible = "winbond,w25q32", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <20000000>;
@ -1915,6 +1916,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&core_vdd_reg>;
};
ahub@70080000 {
@ -1966,7 +1968,7 @@ usb-phy@7d008000 {
status = "okay";
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1985,7 +1987,7 @@ gpled2 {
};
};
vdd_5v_in_reg: regulator@0 {
vdd_5v_in_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v_in";
regulator-min-microvolt = <5000000>;
@ -1993,7 +1995,7 @@ vdd_5v_in_reg: regulator@0 {
regulator-always-on;
};
chargepump_5v_reg: regulator@1 {
chargepump_5v_reg: regulator-chargepump {
compatible = "regulator-fixed";
regulator-name = "chargepump_5v";
regulator-min-microvolt = <5000000>;
@ -2004,7 +2006,7 @@ chargepump_5v_reg: regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
ddr_reg: regulator@2 {
ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
@ -2016,7 +2018,7 @@ ddr_reg: regulator@2 {
vin-supply = <&vdd_5v_in_reg>;
};
vdd_5v_sata_reg: regulator@3 {
vdd_5v_sata_reg: regulator-sata {
compatible = "regulator-fixed";
regulator-name = "vdd_5v_sata";
regulator-min-microvolt = <5000000>;
@ -2028,7 +2030,7 @@ vdd_5v_sata_reg: regulator@3 {
vin-supply = <&vdd_5v_in_reg>;
};
usb1_vbus_reg: regulator@4 {
usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@ -2039,7 +2041,7 @@ usb1_vbus_reg: regulator@4 {
vin-supply = <&vdd_5v_in_reg>;
};
usb3_vbus_reg: regulator@5 {
usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@ -2050,7 +2052,7 @@ usb3_vbus_reg: regulator@5 {
vin-supply = <&vdd_5v_in_reg>;
};
sys_3v3_reg: regulator@6 {
sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3,vdd_3v3_alw";
regulator-min-microvolt = <3300000>;
@ -2062,7 +2064,7 @@ sys_3v3_reg: regulator@6 {
vin-supply = <&vdd_5v_in_reg>;
};
sys_3v3_pexs_reg: regulator@7 {
sys_3v3_pexs_reg: regulator-pexs {
compatible = "regulator-fixed";
regulator-name = "sys_3v3_pexs";
regulator-min-microvolt = <3300000>;
@ -2074,7 +2076,7 @@ sys_3v3_pexs_reg: regulator@7 {
vin-supply = <&sys_3v3_reg>;
};
vdd_5v0_hdmi: regulator@8 {
vdd_5v0_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "+VDD_5V_HDMI";
regulator-min-microvolt = <5000000>;

12
arch/arm/boot/dts/tegra30-cardhu-a02.dts
View File

@ -16,7 +16,7 @@ mmc@78000400 {
keep-power-in-suspend;
};
ddr_reg: regulator@100 {
ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
@ -27,7 +27,7 @@ ddr_reg: regulator@100 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
sys_3v3_reg: regulator@101 {
sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3";
regulator-min-microvolt = <3300000>;
@ -38,7 +38,7 @@ sys_3v3_reg: regulator@101 {
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@102 {
usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@ -49,7 +49,7 @@ usb1_vbus_reg: regulator@102 {
vin-supply = <&vdd_5v0_reg>;
};
usb3_vbus_reg: regulator@103 {
usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@ -60,7 +60,7 @@ usb3_vbus_reg: regulator@103 {
vin-supply = <&vdd_5v0_reg>;
};
vdd_5v0_reg: regulator@104 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
@ -69,7 +69,7 @@ vdd_5v0_reg: regulator@104 {
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
};
vdd_bl_reg: regulator@105 {
vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <5000000>;

14
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View File

@ -16,7 +16,7 @@ mmc@78000400 {
keep-power-in-suspend;
};
ddr_reg: regulator@100 {
ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "ddr";
regulator-min-microvolt = <1500000>;
@ -27,7 +27,7 @@ ddr_reg: regulator@100 {
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
sys_3v3_reg: regulator@101 {
sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3";
regulator-min-microvolt = <3300000>;
@ -38,7 +38,7 @@ sys_3v3_reg: regulator@101 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@102 {
usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@ -49,7 +49,7 @@ usb1_vbus_reg: regulator@102 {
vin-supply = <&vdd_5v0_reg>;
};
usb3_vbus_reg: regulator@103 {
usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@ -60,7 +60,7 @@ usb3_vbus_reg: regulator@103 {
vin-supply = <&vdd_5v0_reg>;
};
vdd_5v0_reg: regulator@104 {
vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
@ -69,7 +69,7 @@ vdd_5v0_reg: regulator@104 {
gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
};
vdd_bl_reg: regulator@105 {
vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <5000000>;
@ -80,7 +80,7 @@ vdd_bl_reg: regulator@105 {
gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
vdd_bl2_reg: regulator@106 {
vdd_bl2_reg: regulator-bl2 {
compatible = "regulator-fixed";
regulator-name = "vdd_bl2";
regulator-min-microvolt = <5000000>;

35
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -175,6 +175,7 @@ serial@70006000 {
serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
status = "okay";
};
@ -209,7 +210,7 @@ i2cmux@70 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
};
};
@ -374,7 +375,8 @@ vdd_core: tps62361@60 {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@1 {
flash@1 {
compatible = "winbond,w25q32", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <20000000>;
@ -391,6 +393,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
ahub@70080000 {
@ -433,7 +436,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -475,7 +478,7 @@ panel: panel {
backlight = <&backlight>;
};
vdd_ac_bat_reg: regulator@0 {
vdd_ac_bat_reg: regulator-acbat {
compatible = "regulator-fixed";
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
@ -483,7 +486,7 @@ vdd_ac_bat_reg: regulator@0 {
regulator-always-on;
};
cam_1v8_reg: regulator@1 {
cam_1v8_reg: regulator-cam {
compatible = "regulator-fixed";
regulator-name = "cam_1v8";
regulator-min-microvolt = <1800000>;
@ -493,7 +496,7 @@ cam_1v8_reg: regulator@1 {
vin-supply = <&vio_reg>;
};
cp_5v_reg: regulator@2 {
cp_5v_reg: regulator-5v0cp {
compatible = "regulator-fixed";
regulator-name = "cp_5v";
regulator-min-microvolt = <5000000>;
@ -504,7 +507,7 @@ cp_5v_reg: regulator@2 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
emmc_3v3_reg: regulator@3 {
emmc_3v3_reg: regulator-emmc {
compatible = "regulator-fixed";
regulator-name = "emmc_3v3";
regulator-min-microvolt = <3300000>;
@ -516,7 +519,7 @@ emmc_3v3_reg: regulator@3 {
vin-supply = <&sys_3v3_reg>;
};
modem_3v3_reg: regulator@4 {
modem_3v3_reg: regulator-modem {
compatible = "regulator-fixed";
regulator-name = "modem_3v3";
regulator-min-microvolt = <3300000>;
@ -525,7 +528,7 @@ modem_3v3_reg: regulator@4 {
gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
};
pex_hvdd_3v3_reg: regulator@5 {
pex_hvdd_3v3_reg: regulator-pex {
compatible = "regulator-fixed";
regulator-name = "pex_hvdd_3v3";
regulator-min-microvolt = <3300000>;
@ -535,7 +538,7 @@ pex_hvdd_3v3_reg: regulator@5 {
vin-supply = <&sys_3v3_reg>;
};
vdd_cam1_ldo_reg: regulator@6 {
vdd_cam1_ldo_reg: regulator-cam1 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam1_ldo";
regulator-min-microvolt = <2800000>;
@ -545,7 +548,7 @@ vdd_cam1_ldo_reg: regulator@6 {
vin-supply = <&sys_3v3_reg>;
};
vdd_cam2_ldo_reg: regulator@7 {
vdd_cam2_ldo_reg: regulator-cam2 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam2_ldo";
regulator-min-microvolt = <2800000>;
@ -555,7 +558,7 @@ vdd_cam2_ldo_reg: regulator@7 {
vin-supply = <&sys_3v3_reg>;
};
vdd_cam3_ldo_reg: regulator@8 {
vdd_cam3_ldo_reg: regulator-cam3 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam3_ldo";
regulator-min-microvolt = <3300000>;
@ -565,7 +568,7 @@ vdd_cam3_ldo_reg: regulator@8 {
vin-supply = <&sys_3v3_reg>;
};
vdd_com_reg: regulator@9 {
vdd_com_reg: regulator-com {
compatible = "regulator-fixed";
regulator-name = "vdd_com";
regulator-min-microvolt = <3300000>;
@ -577,7 +580,7 @@ vdd_com_reg: regulator@9 {
vin-supply = <&sys_3v3_reg>;
};
vdd_fuse_3v3_reg: regulator@10 {
vdd_fuse_3v3_reg: regulator-fuse {
compatible = "regulator-fixed";
regulator-name = "vdd_fuse_3v3";
regulator-min-microvolt = <3300000>;
@ -587,7 +590,7 @@ vdd_fuse_3v3_reg: regulator@10 {
vin-supply = <&sys_3v3_reg>;
};
vdd_pnl1_reg: regulator@11 {
vdd_pnl1_reg: regulator-pnl1 {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl1";
regulator-min-microvolt = <3300000>;
@ -599,7 +602,7 @@ vdd_pnl1_reg: regulator@11 {
vin-supply = <&sys_3v3_reg>;
};
vdd_vid_reg: regulator@12 {
vdd_vid_reg: regulator-vid {
compatible = "regulator-fixed";
regulator-name = "vddio_vid";
regulator-min-microvolt = <5000000>;

25
arch/arm/boot/dts/tegra30-colibri.dtsi
View File

@ -701,10 +701,12 @@ pv0 {
serial@70006040 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
/delete-property/ reg-shift;
};
hdmi_ddc: i2c@7000c700 {
@ -765,9 +767,14 @@ vdd1_reg: vdd1 {
vddctrl_reg: vddctrl {
regulator-name = "+V1.0_VDD_CPU";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
};
reg_1v8_vio: vio {
@ -890,18 +897,20 @@ temp-sensor@4c {
};
/* SW: +V1.2_VDD_CORE */
regulator@60 {
vdd_core: regulator@60 {
compatible = "ti,tps62362";
reg = <0x60>;
regulator-name = "tps62362-vout";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-low;
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
ti,vsel1-state-low;
nvidia,tegra-core-regulator;
};
};
@ -914,6 +923,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
i2c-thermtrip {
@ -951,6 +961,7 @@ usb@7d004000 {
#size-cells = <0>;
asix@1 {
compatible = "usbb95,772b";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
@ -1044,7 +1055,7 @@ sound {
};
&gpio {
lan-reset-n {
lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
output-high;

144
arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi
View File

@ -1,288 +1,288 @@
// SPDX-License-Identifier: GPL-2.0
/ {
cpu0_opp_table: cpu_opp_table0 {
opp@51000000,800 {
cpu0_opp_table: opp-table-cpu0 {
opp-51000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@51000000,850 {
opp-51000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@51000000,912 {
opp-51000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@102000000,800 {
opp-102000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@102000000,850 {
opp-102000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@102000000,912 {
opp-102000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@204000000,800 {
opp-204000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@204000000,850 {
opp-204000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@204000000,912 {
opp-204000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@312000000,850 {
opp-312000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@312000000,912 {
opp-312000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@340000000,800 {
opp-340000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@340000000,850 {
opp-340000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@370000000,800 {
opp-370000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@456000000,850 {
opp-456000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@456000000,912 {
opp-456000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@475000000,800 {
opp-475000000-800 {
opp-microvolt = <800000 800000 1250000>;
};
opp@475000000,850 {
opp-475000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@608000000,850 {
opp-608000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@608000000,912 {
opp-608000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@620000000,850 {
opp-620000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@640000000,850 {
opp-640000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@640000000,900 {
opp-640000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@760000000,850 {
opp-760000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@760000000,900 {
opp-760000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@760000000,912 {
opp-760000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@760000000,975 {
opp-760000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@816000000,850 {
opp-816000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@816000000,912 {
opp-816000000-912 {
opp-microvolt = <912000 912000 1250000>;
};
opp@860000000,850 {
opp-860000000-850 {
opp-microvolt = <850000 850000 1250000>;
};
opp@860000000,900 {
opp-860000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@860000000,975 {
opp-860000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@860000000,1000 {
opp-860000000-1000 {
opp-microvolt = <1000000 1000000 1250000>;
};
opp@910000000,900 {
opp-910000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@1000000000,900 {
opp-1000000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@1000000000,975 {
opp-1000000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@1000000000,1000 {
opp-1000000000-1000 {
opp-microvolt = <1000000 1000000 1250000>;
};
opp@1000000000,1025 {
opp-1000000000-1025 {
opp-microvolt = <1025000 1025000 1250000>;
};
opp@1100000000,900 {
opp-1100000000-900 {
opp-microvolt = <900000 900000 1250000>;
};
opp@1100000000,975 {
opp-1100000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@1100000000,1000 {
opp-1100000000-1000 {
opp-microvolt = <1000000 1000000 1250000>;
};
opp@1100000000,1025 {
opp-1100000000-1025 {
opp-microvolt = <1025000 1025000 1250000>;
};
opp@1100000000,1075 {
opp-1100000000-1075 {
opp-microvolt = <1075000 1075000 1250000>;
};
opp@1150000000,975 {
opp-1150000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@1200000000,975 {
opp-1200000000-975 {
opp-microvolt = <975000 975000 1250000>;
};
opp@1200000000,1000 {
opp-1200000000-1000 {
opp-microvolt = <1000000 1000000 1250000>;
};
opp@1200000000,1025 {
opp-1200000000-1025 {
opp-microvolt = <1025000 1025000 1250000>;
};
opp@1200000000,1050 {
opp-1200000000-1050 {
opp-microvolt = <1050000 1050000 1250000>;
};
opp@1200000000,1075 {
opp-1200000000-1075 {
opp-microvolt = <1075000 1075000 1250000>;
};
opp@1200000000,1100 {
opp-1200000000-1100 {
opp-microvolt = <1100000 1100000 1250000>;
};
opp@1300000000,1000 {
opp-1300000000-1000 {
opp-microvolt = <1000000 1000000 1250000>;
};
opp@1300000000,1025 {
opp-1300000000-1025 {
opp-microvolt = <1025000 1025000 1250000>;
};
opp@1300000000,1050 {
opp-1300000000-1050 {
opp-microvolt = <1050000 1050000 1250000>;
};
opp@1300000000,1075 {
opp-1300000000-1075 {
opp-microvolt = <1075000 1075000 1250000>;
};
opp@1300000000,1100 {
opp-1300000000-1100 {
opp-microvolt = <1100000 1100000 1250000>;
};
opp@1300000000,1125 {
opp-1300000000-1125 {
opp-microvolt = <1125000 1125000 1250000>;
};
opp@1300000000,1150 {
opp-1300000000-1150 {
opp-microvolt = <1150000 1150000 1250000>;
};
opp@1300000000,1175 {
opp-1300000000-1175 {
opp-microvolt = <1175000 1175000 1250000>;
};
opp@1400000000,1100 {
opp-1400000000-1100 {
opp-microvolt = <1100000 1100000 1250000>;
};
opp@1400000000,1125 {
opp-1400000000-1125 {
opp-microvolt = <1125000 1125000 1250000>;
};
opp@1400000000,1150 {
opp-1400000000-1150 {
opp-microvolt = <1150000 1150000 1250000>;
};
opp@1400000000,1175 {
opp-1400000000-1175 {
opp-microvolt = <1175000 1175000 1250000>;
};
opp@1400000000,1237 {
opp-1400000000-1237 {
opp-microvolt = <1237000 1237000 1250000>;
};
opp@1500000000,1125 {
opp-1500000000-1125 {
opp-microvolt = <1125000 1125000 1250000>;
};
opp@1500000000,1150 {
opp-1500000000-1150 {
opp-microvolt = <1150000 1150000 1250000>;
};
opp@1500000000,1200 {
opp-1500000000-1200 {
opp-microvolt = <1200000 1200000 1250000>;
};
opp@1500000000,1237 {
opp-1500000000-1237 {
opp-microvolt = <1237000 1237000 1250000>;
};
opp@1600000000,1212 {
opp-1600000000-1212 {
opp-microvolt = <1212000 1212000 1250000>;
};
opp@1600000000,1237 {
opp-1600000000-1237 {
opp-microvolt = <1237000 1237000 1250000>;
};
opp@1700000000,1212 {
opp-1700000000-1212 {
opp-microvolt = <1212000 1212000 1250000>;
};
opp@1700000000,1237 {
opp-1700000000-1237 {
opp-microvolt = <1237000 1237000 1250000>;
};
};

144
arch/arm/boot/dts/tegra30-cpu-opp.dtsi
View File

@ -1,116 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/ {
cpu0_opp_table: cpu_opp_table0 {
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
opp@51000000,800 {
opp-51000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x31FE>;
opp-hz = /bits/ 64 <51000000>;
};
opp@51000000,850 {
opp-51000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C01>;
opp-hz = /bits/ 64 <51000000>;
};
opp@51000000,912 {
opp-51000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <51000000>;
};
opp@102000000,800 {
opp-102000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x31FE>;
opp-hz = /bits/ 64 <102000000>;
};
opp@102000000,850 {
opp-102000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C01>;
opp-hz = /bits/ 64 <102000000>;
};
opp@102000000,912 {
opp-102000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <102000000>;
};
opp@204000000,800 {
opp-204000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x31FE>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@204000000,850 {
opp-204000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C01>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@204000000,912 {
opp-204000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@312000000,850 {
opp-312000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C00>;
opp-hz = /bits/ 64 <312000000>;
};
opp@312000000,912 {
opp-312000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <312000000>;
};
opp@340000000,800 {
opp-340000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0192>;
opp-hz = /bits/ 64 <340000000>;
};
opp@340000000,850 {
opp-340000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x0F 0x0001>;
opp-hz = /bits/ 64 <340000000>;
};
opp@370000000,800 {
opp-370000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1E 0x306C>;
opp-hz = /bits/ 64 <370000000>;
};
opp@456000000,850 {
opp-456000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C00>;
opp-hz = /bits/ 64 <456000000>;
};
opp@456000000,912 {
opp-456000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <456000000>;
};
opp@475000000,800 {
opp-475000000-800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1E 0x31FE>;
opp-hz = /bits/ 64 <475000000>;
};
opp@475000000,850 {
opp-475000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>,
<0x01 0x0010>, <0x01 0x0080>,
@ -118,25 +118,25 @@ opp@475000000,850 {
opp-hz = /bits/ 64 <475000000>;
};
opp@608000000,850 {
opp-608000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0400>;
opp-hz = /bits/ 64 <608000000>;
};
opp@608000000,912 {
opp-608000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <608000000>;
};
opp@620000000,850 {
opp-620000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1E 0x306C>;
opp-hz = /bits/ 64 <620000000>;
};
opp@640000000,850 {
opp-640000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>,
<0x04 0x0002>, <0x08 0x0002>,
@ -149,13 +149,13 @@ opp@640000000,850 {
opp-hz = /bits/ 64 <640000000>;
};
opp@640000000,900 {
opp-640000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <640000000>;
};
opp@760000000,850 {
opp-760000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>,
<0x08 0x0004>, <0x08 0x0008>,
@ -165,7 +165,7 @@ opp@760000000,850 {
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,900 {
opp-760000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>,
<0x04 0x0002>, <0x02 0x0004>,
@ -177,37 +177,37 @@ opp@760000000,900 {
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,912 {
opp-760000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <760000000>;
};
opp@760000000,975 {
opp-760000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <760000000>;
};
opp@816000000,850 {
opp-816000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0400>;
opp-hz = /bits/ 64 <816000000>;
};
opp@816000000,912 {
opp-816000000-912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <816000000>;
};
opp@860000000,850 {
opp-860000000-850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x0C 0x0001>;
opp-hz = /bits/ 64 <860000000>;
};
opp@860000000,900 {
opp-860000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>,
<0x08 0x0002>, <0x04 0x0004>,
@ -220,7 +220,7 @@ opp@860000000,900 {
opp-hz = /bits/ 64 <860000000>;
};
opp@860000000,975 {
opp-860000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>,
<0x02 0x0004>, <0x02 0x0008>,
@ -229,25 +229,25 @@ opp@860000000,975 {
opp-hz = /bits/ 64 <860000000>;
};
opp@860000000,1000 {
opp-860000000-1000 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <860000000>;
};
opp@910000000,900 {
opp-910000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x18 0x3060>;
opp-hz = /bits/ 64 <910000000>;
};
opp@1000000000,900 {
opp-1000000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x0C 0x0001>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,975 {
opp-1000000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>,
<0x08 0x0002>, <0x04 0x0004>,
@ -260,25 +260,25 @@ opp@1000000000,975 {
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,1000 {
opp-1000000000-1000 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x019E>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1000000000,1025 {
opp-1000000000-1025 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <1000000000>;
};
opp@1100000000,900 {
opp-1100000000-900 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x0001>;
opp-hz = /bits/ 64 <1100000000>;
};
opp@1100000000,975 {
opp-1100000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>,
<0x08 0x0004>, <0x08 0x0008>,
@ -288,7 +288,7 @@ opp@1100000000,975 {
opp-hz = /bits/ 64 <1100000000>;
};
opp@1100000000,1000 {
opp-1100000000-1000 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>,
<0x04 0x0004>, <0x04 0x0008>,
@ -297,31 +297,31 @@ opp@1100000000,1000 {
opp-hz = /bits/ 64 <1100000000>;
};
opp@1100000000,1025 {
opp-1100000000-1025 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x019E>;
opp-hz = /bits/ 64 <1100000000>;
};
opp@1100000000,1075 {
opp-1100000000-1075 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <1100000000>;
};
opp@1150000000,975 {
opp-1150000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x18 0x3060>;
opp-hz = /bits/ 64 <1150000000>;
};
opp@1200000000,975 {
opp-1200000000-975 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x0001>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1000 {
opp-1200000000-1000 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>,
<0x08 0x0004>, <0x08 0x0008>,
@ -331,7 +331,7 @@ opp@1200000000,1000 {
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1025 {
opp-1200000000-1025 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>,
<0x04 0x0004>, <0x04 0x0008>,
@ -340,39 +340,39 @@ opp@1200000000,1025 {
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1050 {
opp-1200000000-1050 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x019E>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1075 {
opp-1200000000-1075 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0001>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1200000000,1100 {
opp-1200000000-1100 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0192>;
opp-hz = /bits/ 64 <1200000000>;
};
opp@1300000000,1000 {
opp-1300000000-1000 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>,
<0x10 0x0100>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1025 {
opp-1300000000-1025 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>,
<0x08 0x0080>, <0x08 0x0100>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1050 {
opp-1300000000-1050 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>,
<0x08 0x0004>, <0x08 0x0008>,
@ -383,68 +383,68 @@ opp@1300000000,1050 {
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1075 {
opp-1300000000-1075 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>,
<0x04 0x0008>, <0x04 0x0010>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1100 {
opp-1300000000-1100 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x001C>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1125 {
opp-1300000000-1125 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0001>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1150 {
opp-1300000000-1150 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0182>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1300000000,1175 {
opp-1300000000-1175 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0010>;
opp-hz = /bits/ 64 <1300000000>;
};
opp@1400000000,1100 {
opp-1400000000-1100 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x18 0x307C>;
opp-hz = /bits/ 64 <1400000000>;
};
opp@1400000000,1125 {
opp-1400000000-1125 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x04 0x000C>;
opp-hz = /bits/ 64 <1400000000>;
};
opp@1400000000,1150 {
opp-1400000000-1150 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>;
opp-hz = /bits/ 64 <1400000000>;
};
opp@1400000000,1175 {
opp-1400000000-1175 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x0010>;
opp-hz = /bits/ 64 <1400000000>;
};
opp@1400000000,1237 {
opp-1400000000-1237 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0010>;
opp-hz = /bits/ 64 <1400000000>;
};
opp@1500000000,1125 {
opp-1500000000-1125 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>,
<0x10 0x0040>, <0x10 0x1000>,
@ -452,7 +452,7 @@ opp@1500000000,1125 {
opp-hz = /bits/ 64 <1500000000>;
};
opp@1500000000,1150 {
opp-1500000000-1150 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>,
<0x08 0x0040>, <0x08 0x1000>,
@ -460,37 +460,37 @@ opp@1500000000,1150 {
opp-hz = /bits/ 64 <1500000000>;
};
opp@1500000000,1200 {
opp-1500000000-1200 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x02 0x0010>;
opp-hz = /bits/ 64 <1500000000>;
};
opp@1500000000,1237 {
opp-1500000000-1237 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x01 0x0010>;
opp-hz = /bits/ 64 <1500000000>;
};
opp@1600000000,1212 {
opp-1600000000-1212 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x10 0x3060>;
opp-hz = /bits/ 64 <1600000000>;
};
opp@1600000000,1237 {
opp-1600000000-1237 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x3060>;
opp-hz = /bits/ 64 <1600000000>;
};
opp@1700000000,1212 {
opp-1700000000-1212 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x10 0x3060>;
opp-hz = /bits/ 64 <1700000000>;
};
opp@1700000000,1237 {
opp-1700000000-1237 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x08 0x3060>;
opp-hz = /bits/ 64 <1700000000>;

8149
arch/arm/boot/dts/tegra30-ouya.dts
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2859
arch/arm/boot/dts/tegra30-pegatron-chagall.dts Normal file
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1756
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
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arch/arm/boot/dts/tegra30.dtsi
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@ -55,6 +55,8 @@ pcie@3000 {
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
power-domains = <&pd_core>;
operating-points-v2 = <&pcie_dvfs_opp_table>;
status = "disabled";
pci@1,0 {
@ -121,9 +123,11 @@ host1x@50000000 {
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
reset-names = "host1x", "mc";
iommus = <&mc TEGRA_SWGROUP_HC>;
power-domains = <&pd_heg>;
operating-points-v2 = <&host1x_dvfs_opp_table>;
#address-cells = <1>;
#size-cells = <1>;
@ -137,8 +141,12 @@ mpe@54040000 {
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
power-domains = <&pd_mpe>;
operating-points-v2 = <&mpe_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_MPE>;
status = "disabled";
};
vi@54080000 {
@ -148,8 +156,12 @@ vi@54080000 {
clocks = <&tegra_car TEGRA30_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
power-domains = <&pd_venc>;
operating-points-v2 = <&vi_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_VI>;
status = "disabled";
};
epp@540c0000 {
@ -159,8 +171,12 @@ epp@540c0000 {
clocks = <&tegra_car TEGRA30_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
power-domains = <&pd_heg>;
operating-points-v2 = <&epp_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_EPP>;
status = "disabled";
};
isp@54100000 {
@ -170,8 +186,11 @@ isp@54100000 {
clocks = <&tegra_car TEGRA30_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
power-domains = <&pd_venc>;
iommus = <&mc TEGRA_SWGROUP_ISP>;
status = "disabled";
};
gr2d@54140000 {
@ -179,8 +198,10 @@ gr2d@54140000 {
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
reset-names = "2d", "mc";
power-domains = <&pd_heg>;
operating-points-v2 = <&gr2d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_G2>;
};
@ -192,8 +213,13 @@ gr3d@54180000 {
<&tegra_car TEGRA30_CLK_GR3D2>;
clock-names = "3d", "3d2";
resets = <&tegra_car 24>,
<&tegra_car 98>;
reset-names = "3d", "3d2";
<&tegra_car 98>,
<&mc TEGRA30_MC_RESET_3D>,
<&mc TEGRA30_MC_RESET_3D2>;
reset-names = "3d", "3d2", "mc", "mc2";
power-domains = <&pd_3d0>, <&pd_3d1>;
power-domain-names = "3d0", "3d1";
operating-points-v2 = <&gr3d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_NV>,
<&mc TEGRA_SWGROUP_NV2>;
@ -208,6 +234,8 @@ dc@54200000 {
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp1_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DC>;
@ -238,6 +266,8 @@ dc@54240000 {
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp2_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DCB>;
@ -268,6 +298,8 @@ hdmi@54280000 {
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
power-domains = <&pd_core>;
operating-points-v2 = <&hdmi_dvfs_opp_table>;
status = "disabled";
};
@ -276,6 +308,8 @@ tvo@542c0000 {
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_TVO>;
power-domains = <&pd_core>;
operating-points-v2 = <&tvo_dvfs_opp_table>;
status = "disabled";
};
@ -287,6 +321,8 @@ dsi@54300000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsia_dvfs_opp_table>;
status = "disabled";
};
@ -298,6 +334,8 @@ dsi@54400000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 84>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsib_dvfs_opp_table>;
status = "disabled";
};
};
@ -358,6 +396,34 @@ tegra_car: clock@60006000 {
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
sclk {
compatible = "nvidia,tegra30-sclk";
clocks = <&tegra_car TEGRA30_CLK_SCLK>;
power-domains = <&pd_core>;
operating-points-v2 = <&sclk_dvfs_opp_table>;
};
pll-c {
compatible = "nvidia,tegra30-pllc";
clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_c_dvfs_opp_table>;
};
pll-e {
compatible = "nvidia,tegra30-plle";
clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_e_dvfs_opp_table>;
};
pll-m {
compatible = "nvidia,tegra30-pllm";
clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_m_dvfs_opp_table>;
};
};
flow-controller@60007000 {
@ -441,9 +507,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 248>;
*/
};
vde@6001a000 {
@ -468,6 +532,8 @@ vde@6001a000 {
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
power-domains = <&pd_vde>;
operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
@ -565,6 +631,8 @@ gmi@70009000 {
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
power-domains = <&pd_core>;
operating-points-v2 = <&nor_dvfs_opp_table>;
status = "disabled";
};
@ -575,6 +643,8 @@ pwm: pwm@7000a000 {
clocks = <&tegra_car TEGRA30_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
power-domains = <&pd_core>;
operating-points-v2 = <&pwm_dvfs_opp_table>;
status = "disabled";
};
@ -666,7 +736,7 @@ i2c@7000d000 {
};
spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000d400 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -676,11 +746,13 @@ spi@7000d400 {
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc1_dvfs_opp_table>;
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000d600 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -690,11 +762,13 @@ spi@7000d600 {
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc2_dvfs_opp_table>;
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000d800 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -704,11 +778,13 @@ spi@7000d800 {
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc3_dvfs_opp_table>;
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000da00 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -718,11 +794,13 @@ spi@7000da00 {
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc4_dvfs_opp_table>;
status = "disabled";
};
spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000dc00 0x200>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -732,11 +810,13 @@ spi@7000dc00 {
reset-names = "spi";
dmas = <&apbdma 27>, <&apbdma 27>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc5_dvfs_opp_table>;
status = "disabled";
};
spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
compatible = "nvidia,tegra30-slink";
reg = <0x7000de00 0x200>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -746,6 +826,8 @@ spi@7000de00 {
reset-names = "spi";
dmas = <&apbdma 28>, <&apbdma 28>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc6_dvfs_opp_table>;
status = "disabled";
};
@ -765,6 +847,72 @@ tegra_pmc: pmc@7000e400 {
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
pd_core: core-domain {
#power-domain-cells = <0>;
operating-points-v2 = <&core_opp_table>;
};
powergates {
pd_3d0: td {
clocks = <&tegra_car TEGRA30_CLK_GR3D>;
resets = <&mc TEGRA30_MC_RESET_3D>,
<&tegra_car TEGRA30_CLK_GR3D>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_3d1: td2 {
clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
resets = <&mc TEGRA30_MC_RESET_3D2>,
<&tegra_car TEGRA30_CLK_GR3D2>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_venc: venc {
clocks = <&tegra_car TEGRA30_CLK_ISP>,
<&tegra_car TEGRA30_CLK_VI>,
<&tegra_car TEGRA30_CLK_CSI>;
resets = <&mc TEGRA30_MC_RESET_ISP>,
<&mc TEGRA30_MC_RESET_VI>,
<&tegra_car TEGRA30_CLK_ISP>,
<&tegra_car 20 /* VI */>,
<&tegra_car TEGRA30_CLK_CSI>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_vde: vdec {
clocks = <&tegra_car TEGRA30_CLK_VDE>;
resets = <&mc TEGRA30_MC_RESET_VDE>,
<&tegra_car TEGRA30_CLK_VDE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_mpe: mpe {
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&mc TEGRA30_MC_RESET_MPE>,
<&tegra_car TEGRA30_CLK_MPE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_heg: heg {
clocks = <&tegra_car TEGRA30_CLK_GR2D>,
<&tegra_car TEGRA30_CLK_EPP>,
<&tegra_car TEGRA30_CLK_HOST1X>;
resets = <&mc TEGRA30_MC_RESET_2D>,
<&mc TEGRA30_MC_RESET_EPP>,
<&mc TEGRA30_MC_RESET_HC>,
<&tegra_car TEGRA30_CLK_GR2D>,
<&tegra_car TEGRA30_CLK_EPP>,
<&tegra_car TEGRA30_CLK_HOST1X>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};
mc: memory-controller@7000f000 {
@ -785,6 +933,7 @@ emc: memory-controller@7000f400 {
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
power-domains = <&pd_core>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
@ -799,6 +948,8 @@ fuse@7000f800 {
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
power-domains = <&pd_core>;
operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
};
tsensor: tsensor@70014000 {
@ -921,6 +1072,8 @@ mmc@78000000 {
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
status = "disabled";
};
@ -943,6 +1096,8 @@ mmc@78000400 {
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
status = "disabled";
};
@ -967,6 +1122,8 @@ usb@7d000000 {
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
power-domains = <&pd_core>;
operating-points-v2 = <&usbd_dvfs_opp_table>;
status = "disabled";
};
@ -1008,6 +1165,8 @@ usb@7d004000 {
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb2_dvfs_opp_table>;
status = "disabled";
};
@ -1048,6 +1207,8 @@ usb@7d008000 {
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb3_dvfs_opp_table>;
status = "disabled";
};