github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-07 06:17:02 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: qcom: Add support for camera clock controller on Maili

Browse Source 
Maili camcc is mostly identical to Hawi camcc, with a few clocks
removed, frequency table updates for a few other clocks, and PLL
configuration changes. Hence, reuse the Hawi camera clock controller
driver and extend it for the Qualcomm Maili SoC.

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260922-maili_camcc-v4-2-87704b664dde@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jagadeesh Kona 2026-09-22 09:26:38 +05:30 committed by Bjorn Andersson
parent 104480aa66
commit 5c32769895
1 changed files with 159 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

159
drivers/clk/qcom/camcc-hawi.c
View File

@ -66,6 +66,18 @@ static const struct alpha_pll_config cam_cc_pll0_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 1200.0 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll0_config_maili = {
.l = 0x3e,
.cal_l = 0x42,
.alpha = 0x8000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.config = &cam_cc_pll0_config,
@ -141,6 +153,18 @@ static const struct alpha_pll_config cam_cc_pll1_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 493.2 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll1_config_maili = {
.l = 0x19,
.cal_l = 0x42,
.alpha = 0xb000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.config = &cam_cc_pll1_config,
@ -193,6 +217,18 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 600.0 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll2_config_maili = {
.l = 0x1f,
.cal_l = 0x42,
.alpha = 0x4000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.config = &cam_cc_pll2_config,
@ -245,6 +281,18 @@ static const struct alpha_pll_config cam_cc_pll3_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 476.4 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll3_config_maili = {
.l = 0x18,
.cal_l = 0x42,
.alpha = 0xd000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.config = &cam_cc_pll3_config,
@ -297,6 +345,18 @@ static const struct alpha_pll_config cam_cc_pll4_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 476.4 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll4_config_maili = {
.l = 0x18,
.cal_l = 0x42,
.alpha = 0xd000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.config = &cam_cc_pll4_config,
@ -349,6 +409,18 @@ static const struct alpha_pll_config cam_cc_pll5_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 476.4 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll5_config_maili = {
.l = 0x18,
.cal_l = 0x42,
.alpha = 0xd000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.config = &cam_cc_pll5_config,
@ -401,6 +473,18 @@ static const struct alpha_pll_config cam_cc_pll6_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 960.0 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll6_config_maili = {
.l = 0x32,
.cal_l = 0x42,
.alpha = 0x0,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.config = &cam_cc_pll6_config,
@ -476,6 +560,18 @@ static const struct alpha_pll_config cam_cc_pll7_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 345.0 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll7_config_maili = {
.l = 0x11,
.cal_l = 0x42,
.alpha = 0xf800,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll7 = {
.offset = 0x7000,
.config = &cam_cc_pll7_config,
@ -505,6 +601,18 @@ static const struct alpha_pll_config cam_cc_pll8_config = {
.user_ctl_hi_val = 0x00000002,
};
/* 493.2 MHz Configuration */
static const struct alpha_pll_config cam_cc_pll8_config_maili = {
.l = 0x19,
.cal_l = 0x42,
.alpha = 0xb000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll cam_cc_pll8 = {
.offset = 0x8000,
.config = &cam_cc_pll8_config,
@ -682,6 +790,17 @@ static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src_maili[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = {
.cmd_rcgr = 0x212cc,
.mnd_width = 0,
@ -703,6 +822,11 @@ static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src_maili[] = {
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0x21250,
.mnd_width = 8,
@ -1076,6 +1200,17 @@ static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_cam_cc_ofe_clk_src_maili[] = {
F(300000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(376000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(445000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(500000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(609000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ofe_clk_src = {
.cmd_rcgr = 0x20120,
.mnd_width = 0,
@ -2970,12 +3105,36 @@ static const struct qcom_cc_desc cam_cc_hawi_desc = {
static const struct of_device_id cam_cc_hawi_match_table[] = {
{ .compatible = "qcom,hawi-camcc" },
{ .compatible = "qcom,maili-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_hawi_match_table);
static int cam_cc_hawi_probe(struct platform_device *pdev)
{
if (device_is_compatible(&pdev->dev, "qcom,maili-camcc")) {
cam_cc_pll0.config = &cam_cc_pll0_config_maili;
cam_cc_pll1.config = &cam_cc_pll1_config_maili;
cam_cc_pll2.config = &cam_cc_pll2_config_maili;
cam_cc_pll3.config = &cam_cc_pll3_config_maili;
cam_cc_pll4.config = &cam_cc_pll4_config_maili;
cam_cc_pll5.config = &cam_cc_pll5_config_maili;
cam_cc_pll6.config = &cam_cc_pll6_config_maili;
cam_cc_pll7.config = &cam_cc_pll7_config_maili;
cam_cc_pll8.config = &cam_cc_pll8_config_maili;
cam_cc_camnoc_rt_axi_clk_src.freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src_maili;
cam_cc_cci_0_clk_src.freq_tbl = ftbl_cam_cc_cci_0_clk_src_maili;
cam_cc_cci_1_clk_src.freq_tbl = ftbl_cam_cc_cci_0_clk_src_maili;
cam_cc_ofe_clk_src.freq_tbl = ftbl_cam_cc_ofe_clk_src_maili;
cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK_SRC] = NULL;
cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK] = NULL;
cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK_SRC] = NULL;
cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK] = NULL;
cam_cc_hawi_clocks[CAM_CC_CSIPHY5_CLK] = NULL;
}
return qcom_cc_probe(pdev, &cam_cc_hawi_desc);
}