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wifi: rtw89: add C2H RA event V1 to support WiFi 7 chips

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WiFi 7 chips have more rate mode (EHT), higher MCS and more bandwidth, so
define and use reserved bits to carry these information in C2H events.
Also, the SS/MCS encoded bits of VHT and HE are changed, so define V1 masks
for them.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230728070252.66525-9-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2023-07-28 15:02:50 +08:00 committed by Kalle Valo
parent 57cafeb18f
commit 5c152231c3
3 changed files with 41 additions and 8 deletions
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2
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -587,6 +587,8 @@ enum rtw89_hw_rate {
RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
};
/* 2G channels,

12
drivers/net/wireless/realtek/rtw89/fw.h
View File

@ -3168,16 +3168,24 @@ struct rtw89_c2h_ra_rpt {
#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
#define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
#define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
#define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
/* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
* HT-new: [6:5]: NA, [4:0]: MCS
/* For WiFi 6 chips:
* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
* HT-new: [6:5]: NA, [4:0]: MCS
* For WiFi 7 chips (V1):
* HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
*/
#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
FIELD_PREP(GENMASK(2, 0), mcs))

35
drivers/net/wireless/realtek/rtw89/phy.c
View File

@ -2247,10 +2247,13 @@ static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
const struct rtw89_c2h_ra_rpt *c2h =
(const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
struct rtw89_ra_report *ra_report = &rtwsta->ra_report;
const struct rtw89_chip_info *chip = rtwdev->chip;
bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
u8 mode, rate, bw, giltf, mac_id;
u16 legacy_bitrate;
bool valid;
u8 mcs = 0;
u8 t;
mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
if (mac_id != rtwsta->mac_id)
@ -2261,6 +2264,15 @@ static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
if (format_v1) {
t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
rate |= u8_encode_bits(t, BIT(7));
t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
bw |= u8_encode_bits(t, BIT(2));
t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
mode |= u8_encode_bits(t, BIT(2));
}
if (mode == RTW89_RA_RPT_MODE_LEGACY) {
valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
if (!valid)
@ -2287,16 +2299,24 @@ static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
break;
case RTW89_RA_RPT_MODE_VHT:
ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
ra_report->txrate.mcs = format_v1 ?
u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
ra_report->txrate.nss = format_v1 ?
u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
if (giltf)
ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
mcs = ra_report->txrate.mcs;
break;
case RTW89_RA_RPT_MODE_HE:
ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
ra_report->txrate.mcs = format_v1 ?
u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
ra_report->txrate.nss = format_v1 ?
u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
@ -2309,8 +2329,11 @@ static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) |
FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate);
ra_report->hw_rate = format_v1 ?
u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
ra_report->might_fallback_legacy = mcs <= 2;
sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1;