From 08a7d82b612e10742cb66553ad8ecae99ef70295 Mon Sep 17 00:00:00 2001 From: Xubin Bai Date: Wed, 22 Jun 2022 10:40:45 -0700 Subject: [PATCH 1/2] clk: qcom: rpmh: Add support for RPMH clocks for Pineapple Add clock rpmh data to communicate with RPMH clocks for Pineapple. Change-Id: I13bcf5623595e69addea70a52d902e15d9977550 Signed-off-by: Xubin Bai --- drivers/clk/qcom/clk-rpmh.c | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6a73accd18ad..149d9d1ce762 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -680,6 +680,46 @@ static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, return rpmh->clks[idx]; } +DEFINE_CLK_RPMH_ARC(pineapple, xo_pad, xo_pad_ao, "xo.lvl", 0x03, 2); +DEFINE_CLK_RPMH_FIXED(pineapple, bi_tcxo, bi_tcxo_ao, xo_pad, xo_pad_ao, 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, rf_clk1, rf_clk1_ao, "clka1", 1); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, rf_clk2, rf_clk2_ao, "clka2", 1); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, rf_clk3, rf_clk3_ao, "clka3", 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, rf_clk4, rf_clk4_ao, "clka4", 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, rf_clk5, rf_clk5_ao, "clka5", 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, ln_bb_clk1, ln_bb_clk1_ao, "clka6", 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, ln_bb_clk2, ln_bb_clk2_ao, "clka7", 2); +DEFINE_CLK_RPMH_VRM_OPT(pineapple, ln_bb_clk3, ln_bb_clk3_ao, "clka8", 2); + +static struct clk_hw *pineapple_rpmh_clocks[] = { + [RPMH_CXO_PAD_CLK] = &pineapple_xo_pad.hw, + [RPMH_CXO_PAD_CLK_A] = &pineapple_xo_pad_ao.hw, + [RPMH_CXO_CLK] = &pineapple_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &pineapple_bi_tcxo_ao.hw, + [RPMH_LN_BB_CLK1] = &pineapple_ln_bb_clk1.hw, + [RPMH_LN_BB_CLK1_A] = &pineapple_ln_bb_clk1_ao.hw, + [RPMH_LN_BB_CLK2] = &pineapple_ln_bb_clk2.hw, + [RPMH_LN_BB_CLK2_A] = &pineapple_ln_bb_clk2_ao.hw, + [RPMH_LN_BB_CLK3] = &pineapple_ln_bb_clk3.hw, + [RPMH_LN_BB_CLK3_A] = &pineapple_ln_bb_clk3_ao.hw, + [RPMH_RF_CLK1] = &pineapple_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &pineapple_rf_clk1_ao.hw, + [RPMH_RF_CLK2] = &pineapple_rf_clk2.hw, + [RPMH_RF_CLK2_A] = &pineapple_rf_clk2_ao.hw, + [RPMH_RF_CLK3] = &pineapple_rf_clk3.hw, + [RPMH_RF_CLK3_A] = &pineapple_rf_clk3_ao.hw, + [RPMH_RF_CLK4] = &pineapple_rf_clk4.hw, + [RPMH_RF_CLK4_A] = &pineapple_rf_clk4_ao.hw, + [RPMH_RF_CLK5] = &pineapple_rf_clk5.hw, + [RPMH_RF_CLK5_A] = &pineapple_rf_clk5_ao.hw, + [RPMH_IPA_CLK] = &sdm845_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_pineapple = { + .clks = pineapple_rpmh_clocks, + .num_clks = ARRAY_SIZE(pineapple_rpmh_clocks), +}; + static int clk_rpmh_probe(struct platform_device *pdev) { struct clk_hw **hw_clks; @@ -767,6 +807,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, + { .compatible = "qcom,pineapple-rpmh-clk", .data = &clk_rpmh_pineapple}, { } }; MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); From cacc6a2e75171dd910ae96f58a37912c5fe2d9e9 Mon Sep 17 00:00:00 2001 From: Xubin Bai Date: Wed, 22 Jun 2022 10:43:42 -0700 Subject: [PATCH 2/2] defconfig: pineapple-gki: Enable RPMH clock driver Enable RPMh clock driver so consumers can vote for actual RPMH clocks. Change-Id: I3e1e10e930df46501bf95fbc2ac7a0e18391f667 Signed-off-by: Xubin Bai --- arch/arm64/configs/vendor/pineapple_GKI.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/pineapple_GKI.config b/arch/arm64/configs/vendor/pineapple_GKI.config index e1740947ae2b..33ee8846e4c5 100644 --- a/arch/arm64/configs/vendor/pineapple_GKI.config +++ b/arch/arm64/configs/vendor/pineapple_GKI.config @@ -20,6 +20,7 @@ CONFIG_PHY_QCOM_UFS_QRBTC_SDM845=m CONFIG_PINCTRL_MSM=m CONFIG_PINCTRL_PINEAPPLE=m CONFIG_POWER_RESET_QCOM_REBOOT_REASON=m +CONFIG_QCOM_CLK_RPMH=m CONFIG_QCOM_COMMAND_DB=m CONFIG_QCOM_DMABUF_HEAPS=m CONFIG_QCOM_DMABUF_HEAPS_CARVEOUT=y