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net: pcs: xpcs: correctly place DW_VR_MII_DIG_CTRL1_2G5_EN
Place DW_VR_MII_DIG_CTRL1_2G5_EN with the other DW_VR_MII_DIG_CTRL1 definitions rather than in the middle of a register list. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -60,8 +60,6 @@
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#define DW_VR_MII_DIG_CTRL1 0x8000
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#define DW_VR_MII_AN_CTRL 0x8001
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#define DW_VR_MII_AN_INTR_STS 0x8002
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/* Enable 2.5G Mode */
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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/* EEE Mode Control Register */
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#define DW_VR_MII_EEE_MCTRL0 0x8006
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#define DW_VR_MII_EEE_MCTRL1 0x800b
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@ -69,6 +67,7 @@
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/* VR_MII_DIG_CTRL1 */
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#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
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/* VR_MII_DIG_CTRL2 */
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