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drm/amdgpu/vcn4.0.3: read back register after written

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The addition of register read-back in VCN v4.0.3 is intended to prevent
potential race conditions.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David (Ming Qiang) Wu 2025-05-14 18:55:59 -04:00 committed by Alex Deucher
parent a3810a5e37
commit 5b4c6413c8
1 changed files with 16 additions and 0 deletions
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16
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
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@ -977,6 +977,11 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
/*resetting done, fw can check RB ring */
fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
return 0;
}
@ -1370,6 +1375,12 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
/* disable dynamic power gating mode */
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
return 0;
}
@ -1453,6 +1464,11 @@ static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst)
/* apply HW clock gating */
vcn_v4_0_3_enable_clock_gating(vinst);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
Done:
return 0;
}