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wifi: rtw89: 8851b: rfk: update TX wideband IQK
Adjust TX wideband calibration from 1 to 2 loop gain settings. This can reflect in better performance in 5 GHz medium-high attenuation environments. Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20250811123913.15524-1-pkshih@realtek.com
This commit is contained in:
Kuan-Chung Chen
Ping-Ke Shih
parent
b521685da3
commit
5b2341efbb
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@ -9126,6 +9126,7 @@
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#define B_COEF_SEL_MDPD BIT(8)
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#define B_COEF_SEL_MDPD_V1 GENMASK(9, 8)
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#define B_COEF_SEL_EN BIT(31)
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#define R_CFIR_COEF 0x810c
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#define R_CFIR_SYS 0x8120
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#define R_IQK_RES 0x8124
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#define B_IQK_RES_K BIT(28)
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@ -18,7 +18,8 @@
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#define DPK_KSET_NUM 4
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#define RTW8851B_RXK_GROUP_NR 4
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#define RTW8851B_RXK_GROUP_IDX_NR 4
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#define RTW8851B_TXK_GROUP_NR 1
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#define RTW8851B_A_TXK_GROUP_NR 2
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#define RTW8851B_G_TXK_GROUP_NR 1
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#define RTW8851B_IQK_VER 0x14
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#define RTW8851B_IQK_SS 1
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#define RTW8851B_LOK_GRAM 10
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@ -117,16 +118,18 @@ static const u32 g_idxrxagc[RTW8851B_RXK_GROUP_NR] = {0x0, 0x1, 0x2, 0x3};
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static const u32 a_idxrxgain[RTW8851B_RXK_GROUP_IDX_NR] = {0x10C, 0x112, 0x28c, 0x292};
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static const u32 a_idxattc2[RTW8851B_RXK_GROUP_IDX_NR] = {0xf, 0xf, 0xf, 0xf};
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static const u32 a_idxrxagc[RTW8851B_RXK_GROUP_IDX_NR] = {0x4, 0x5, 0x6, 0x7};
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static const u32 a_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
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static const u32 a_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
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static const u32 a_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x0a};
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static const u32 a_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
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static const u32 g_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
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static const u32 g_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
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static const u32 g_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x10};
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static const u32 g_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
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static const u32 a_power_range[RTW8851B_A_TXK_GROUP_NR] = {0x0, 0x0};
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static const u32 a_track_range[RTW8851B_A_TXK_GROUP_NR] = {0x7, 0x7};
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static const u32 a_gain_bb[RTW8851B_A_TXK_GROUP_NR] = {0x08, 0x0d};
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static const u32 a_itqt[RTW8851B_A_TXK_GROUP_NR] = {0x12, 0x12};
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static const u32 a_att_smxr[RTW8851B_A_TXK_GROUP_NR] = {0x0, 0x2};
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static const u32 g_power_range[RTW8851B_G_TXK_GROUP_NR] = {0x0};
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static const u32 g_track_range[RTW8851B_G_TXK_GROUP_NR] = {0x6};
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static const u32 g_gain_bb[RTW8851B_G_TXK_GROUP_NR] = {0x10};
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static const u32 g_itqt[RTW8851B_G_TXK_GROUP_NR] = {0x12};
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static const u32 rtw8851b_backup_bb_regs[] = {0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8};
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static const u32 rtw8851b_backup_bb_regs[] = {
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0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8, 0x12a0, 0xc0f0};
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static const u32 rtw8851b_backup_rf_regs[] = {
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0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
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@ -789,7 +792,7 @@ static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
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"[IQK]============ S%d ID_NBTXK ============\n", path);
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rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT,
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0x00b);
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0x11);
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iqk_cmd = 0x408 | (1 << (4 + path));
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break;
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case ID_NBRXK:
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@ -807,7 +810,7 @@ static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
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rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
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notready = _iqk_check_cal(rtwdev, path);
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if (iqk_info->iqk_sram_en &&
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(ktype == ID_NBRXK || ktype == ID_RXK))
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(ktype == ID_NBRXK || ktype == ID_RXK || ktype == ID_NBTXK))
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_iqk_sram(rtwdev, path);
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rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
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@ -1174,6 +1177,7 @@ static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
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static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, u8 path)
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{
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static const u8 a_idx[RTW8851B_A_TXK_GROUP_NR] = {2, 3};
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struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
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bool kfail = false;
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bool notready;
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@ -1181,16 +1185,20 @@ static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev,
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
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for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
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rtw89_phy_write32_mask(rtwdev, R_CFIR_COEF, MASKDWORD, 0x33332222);
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for (gp = 0x0; gp < RTW8851B_A_TXK_GROUP_NR; gp++) {
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
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rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, a_att_smxr[gp]);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, a_idx[gp]);
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rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
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rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x11);
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rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
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notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
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@ -1231,7 +1239,9 @@ static bool _txk_2g_group_sel(struct rtw89_dev *rtwdev,
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
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for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
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rtw89_phy_write32_mask(rtwdev, R_CFIR_COEF, MASKDWORD, 0x0);
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for (gp = 0x0; gp < RTW8851B_G_TXK_GROUP_NR; gp++) {
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
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@ -1274,29 +1284,29 @@ static bool _txk_2g_group_sel(struct rtw89_dev *rtwdev,
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static bool _iqk_5g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
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u8 path)
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{
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static const u8 a_idx[RTW8851B_A_TXK_GROUP_NR] = {2, 3};
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struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
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bool kfail = false;
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bool notready;
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u8 gp;
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u8 gp = 0;
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
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for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
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rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, a_att_smxr[gp]);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
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rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
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rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, a_idx[gp]);
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rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
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rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
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notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
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iqk_info->nb_txcfir[path] =
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rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
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}
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notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
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iqk_info->nb_txcfir[path] =
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rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
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if (!notready)
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kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
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@ -1325,7 +1335,7 @@ static bool _iqk_2g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
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for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
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for (gp = 0x0; gp < RTW8851B_G_TXK_GROUP_NR; gp++) {
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
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rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
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