From 5af7a8a522f61ae2a3e5038c889e231e56d63526 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Mon, 22 Jun 2026 06:54:10 +0000 Subject: [PATCH] arm64: tegra: Fix CMDQV interrupt type on Tegra264 The CMDQV interrupts on Tegra264 are described as level-triggered, but per the hardware interrupt documentation these interrupts are actually edge-triggered. Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH to IRQ_TYPE_EDGE_RISING. Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV") Reported-by: Nicolin Chen Signed-off-by: Ashish Mhetre Acked-by: Jon Hunter Acked-by: Nicolin Chen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 42b143155ed4..4073e3905f81 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3413,7 +3413,7 @@ smmu1: iommu@5000000 { cmdqv1: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x5200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3433,7 +3433,7 @@ smmu2: iommu@6000000 { cmdqv2: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3506,7 +3506,7 @@ smmu0: iommu@a000000 { cmdqv0: cmdqv@a200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xa200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3526,7 +3526,7 @@ smmu4: iommu@b000000 { cmdqv4: cmdqv@b200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xb200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3914,7 +3914,7 @@ smmu3: iommu@6000000 { cmdqv3: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; };