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drm/i915/pxp: Add MTL hw-plumbing enabling for KCR operation

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Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:

1. Updating 'pick-gt' to get the media tile for
   KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
   (init, status-checking, etc.).

While doing #2, lets create a separate registers header file for PXP
to be consistent with other i915 global subsystems.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230511231738.1077674-3-alan.previn.teres.alexis@intel.com
This commit is contained in:
Alan Previn 2023-05-11 16:17:32 -07:00 committed by Radhakrishna Sripada
parent d6bf74de07
commit 5adacf19f6
5 changed files with 59 additions and 23 deletions
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3
drivers/gpu/drm/i915/gt/intel_gt_irq.c
View File

@ -106,7 +106,8 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
case OTHER_CLASS:
if (instance == OTHER_GSC_HECI_2_INSTANCE)
return media_gt;
if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) &&
HAS_ENGINE(media_gt, GSC0))
return media_gt;
fallthrough;
default:

34
drivers/gpu/drm/i915/pxp/intel_pxp.c
View File

@ -14,6 +14,7 @@
#include "intel_pxp.h"
#include "intel_pxp_gsccs.h"
#include "intel_pxp_irq.h"
#include "intel_pxp_regs.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
@ -61,21 +62,22 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp)
return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid;
}
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
static void kcr_pxp_enable(struct intel_gt *gt)
static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
{
intel_uncore_write(gt->uncore, KCR_INIT,
_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
}
static void kcr_pxp_disable(struct intel_gt *gt)
static void kcr_pxp_enable(const struct intel_pxp *pxp)
{
intel_uncore_write(gt->uncore, KCR_INIT,
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
kcr_pxp_set_status(pxp, true);
}
static void kcr_pxp_disable(const struct intel_pxp *pxp)
{
kcr_pxp_set_status(pxp, false);
}
static int create_vcs_context(struct intel_pxp *pxp)
@ -127,6 +129,11 @@ static void pxp_init_full(struct intel_pxp *pxp)
init_completion(&pxp->termination);
complete_all(&pxp->termination);
if (pxp->ctrl_gt->type == GT_MEDIA)
pxp->kcr_base = MTL_KCR_BASE;
else
pxp->kcr_base = GEN12_KCR_BASE;
intel_pxp_session_management_init(pxp);
ret = create_vcs_context(pxp);
@ -369,14 +376,13 @@ int intel_pxp_start(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp->ctrl_gt);
kcr_pxp_enable(pxp);
intel_pxp_irq_enable(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
{
kcr_pxp_disable(pxp->ctrl_gt);
kcr_pxp_disable(pxp);
intel_pxp_irq_disable(pxp);
}

27
drivers/gpu/drm/i915/pxp/intel_pxp_regs.h Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright(c) 2023, Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_PXP_REGS_H__
#define __INTEL_PXP_REGS_H__
#include "i915_reg_defs.h"
/* KCR subsystem register base address */
#define GEN12_KCR_BASE 0x32000
#define MTL_KCR_BASE 0x386000
/* KCR enable/disable control */
#define KCR_INIT(base) _MMIO((base) + 0xf0)
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
/* KCR hwdrm session in play status 0-31 */
#define KCR_SIP(base) _MMIO((base) + 0x260)
/* PXP global terminate register for session termination */
#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
#endif /* __INTEL_PXP_REGS_H__ */

12
drivers/gpu/drm/i915/pxp/intel_pxp_session.c
View File

@ -10,14 +10,10 @@
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
#include "intel_pxp_regs.h"
#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
/* PXP global terminate register for session termination */
#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
{
struct intel_uncore *uncore = pxp->ctrl_gt->uncore;
@ -26,7 +22,7 @@ static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
/* if we're suspended the session is considered off */
with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
sip = intel_uncore_read(uncore, KCR_SIP(pxp->kcr_base));
return sip & BIT(id);
}
@ -44,7 +40,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla
return in_play ? -ENODEV : 0;
ret = intel_wait_for_register(uncore,
GEN12_KCR_SIP,
KCR_SIP(pxp->kcr_base),
mask,
in_play ? mask : 0,
100);
@ -108,7 +104,7 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
return ret;
}
intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
intel_uncore_write(gt->uncore, KCR_GLOBAL_TERMINATE(pxp->kcr_base), 1);
intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);

6
drivers/gpu/drm/i915/pxp/intel_pxp_types.h
View File

@ -26,6 +26,12 @@ struct intel_pxp {
*/
struct intel_gt *ctrl_gt;
/**
* @kcr_base: base mmio offset for the KCR engine which is different on legacy platforms
* vs newer platforms where the KCR is inside the media-tile.
*/
u32 kcr_base;
/**
* @gsccs_res: resources for request submission for platforms that have a GSC engine.
*/