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drm/amd/display: Added visual confirm for DCC

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[WHY]
We want to add a visual confirm mode for DCC and MCache for
debugging purpose.

[HOW]
color pipes based on whether DCC is enabled and what MCache id
is used.
black - DCC disabled
red - DCC enabled
grey - 2 different MCaches used
other colors - 1 MCache used

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Leo Zeng <Leo.Zeng@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Zeng 2025-02-19 10:29:39 -05:00 committed by Alex Deucher
parent c707ea82c7
commit 5ad8eed172
4 changed files with 59 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -1202,6 +1202,8 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte
get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR)
get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_DCC)
get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));
else {
if (dc->ctx->dce_version < DCN_VERSION_2_0)
color_space_to_black_color(
@ -3956,6 +3958,9 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type == UPDATE_TYPE_FULL && dc->optimized_required)
hwss_process_outstanding_hw_updates(dc, dc->current_state);
if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)
dc->res_pool->funcs->prepare_mcache_programming(dc, context);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@ -4014,9 +4019,6 @@ static void commit_planes_for_stream(struct dc *dc,
odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
}
if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)
dc->res_pool->funcs->prepare_mcache_programming(dc, context);
if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

48
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
View File

@ -34,6 +34,7 @@
#include "dc_state_priv.h"
#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
#define MAX_NUM_MCACHE 8
/* used as index in array of black_color_format */
enum black_color_format {
@ -553,6 +554,53 @@ void get_cursor_visual_confirm_color(
}
}
void get_dcc_visual_confirm_color(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
{
const uint32_t MCACHE_ID_UNASSIGNED = 0xF;
if (!pipe_ctx->plane_state->dcc.enable) {
color->color_r_cr = 0; /* black - DCC disabled */
color->color_g_y = 0;
color->color_b_cb = 0;
return;
}
if (dc->ctx->dce_version < DCN_VERSION_4_01) {
color->color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */
color->color_g_y = 0;
color->color_b_cb = 0;
return;
}
uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;
uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;
if (first_id != MCACHE_ID_UNASSIGNED && second_id != MCACHE_ID_UNASSIGNED && first_id != second_id) {
color->color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */
color->color_g_y = MAX_TG_COLOR_VALUE/2;
color->color_b_cb = MAX_TG_COLOR_VALUE/2;
}
else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) {
const struct tg_color id_colors[MAX_NUM_MCACHE] = {
{0, MAX_TG_COLOR_VALUE, 0}, /* green */
{0, 0, MAX_TG_COLOR_VALUE}, /* blue */
{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
{0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */
{MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */
{0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */
};
uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;
*color = id_colors[assigned_id];
}
}
void set_p_state_switch_method(
struct dc *dc,
struct dc_state *context,

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -495,6 +495,7 @@ enum visual_confirm {
VISUAL_CONFIRM_FAMS2 = 19,
VISUAL_CONFIRM_HW_CURSOR = 20,
VISUAL_CONFIRM_VABC = 21,
VISUAL_CONFIRM_DCC = 22,
};
enum dc_psr_power_opts {

5
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
View File

@ -517,6 +517,11 @@ void get_cursor_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
void get_dcc_visual_confirm_color(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
void set_p_state_switch_method(
struct dc *dc,
struct dc_state *context,