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drm/amdgpu: Support forcing MTYPE_RW

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Set default value of module parameter amdgpu_mtype_local to -1. This
allows to force MTYPE_RW on ASICs where MTYPE_RW is not default.

v2: Fix SDMA get_vm_pte_pde MTYPE

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harish Kasiviswanathan 2026-02-14 18:28:28 -05:00 committed by Alex Deucher
parent f6e9582a7f
commit 5abc46d134
4 changed files with 26 additions and 14 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -839,8 +839,8 @@ module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_evictio
/**
* DOC: mtype_local (int)
*/
int amdgpu_mtype_local;
MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
int amdgpu_mtype_local = -1;
MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)");
module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
/**

9
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
View File

@ -534,13 +534,16 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev,
mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC;
mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC;
if (amdgpu_mtype_local == 1) {
if (amdgpu_mtype_local == 0) {
DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
mtype_local = MTYPE_RW;
} else if (amdgpu_mtype_local == 1) {
DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
mtype_local = MTYPE_NC;
} else if (amdgpu_mtype_local == 2) {
DRM_INFO_ONCE("MTYPE_CC not supported, using MTYPE_RW instead for local memory\n");
DRM_INFO_ONCE("MTYPE_CC not supported, using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC");
} else {
DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
DRM_INFO_ONCE("Using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC");
}
is_local = (is_vram && adev == bo_adev);

21
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
View File

@ -1129,12 +1129,21 @@ static void sdma_v7_1_vm_set_pte_pde(struct amdgpu_ib *ib,
/* for physically contiguous pages (vram) */
u32 header = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
if (amdgpu_mtype_local)
header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3);
else
header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2) |
SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) |
SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3));
/* TODO:
* When VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is enabled, change below MTYPE
* to RW for AID A1 and UC for AID A0. NC needs additional GCR flush and need not
* be supported. Also, honour amdgpu_mtype_local override. RW would additionally
* require setting SCOPE bits in the header.
*
* header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2:RW) |
* SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) |
* SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3:SYS_SCOPE));
*/
/* VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is 0 which defaults to UC. So,
* use MTYPE_UC (0x3). For ref. MTYPE_RW=0x2 MTYPE_NC=0x0
*/
header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3) | SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1);
ib->ptr[ib->length_dw++] = header;
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

6
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
View File

@ -1311,9 +1311,9 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm,
bool is_local = (domain == SVM_RANGE_VRAM_DOMAIN) &&
(bo_node->adev == node->adev);
mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC :
is_aid_a1 ?
AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC;
mtype_local = amdgpu_mtype_local == 0 ? AMDGPU_VM_MTYPE_RW :
amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC :
is_aid_a1 ? AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC;
mtype_remote = is_aid_a1 ? AMDGPU_VM_MTYPE_NC : AMDGPU_VM_MTYPE_UC;
snoop = true;