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PCI: dwc: Replace certain BAR_RESERVED with BAR_DISABLED in glue drivers

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Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
ep->ops->init(). (The only exception is pci-keystone.c.)

An EPF driver will be able to get/enable BARs that have been disabled/reset
using dw_pcie_ep_reset_bar(), except if the BAR is marked as BAR_RESERVED
(see pci_epc_get_next_free_bar()).

Thus, all EPC drivers that have BARs marked as BAR_RESERVED in epc_features
and call dw_pcie_ep_reset_bar(), should really have these BARs marked as
BAR_DISABLED. If dw_pcie_ep_reset_bar() is not called by the glue driver,
the BARs are kept as BAR_RESERVED.

No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: Koichiro Den <den@valinux.co.jp>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260312130229.2282001-18-cassel@kernel.org
This commit is contained in:
Niklas Cassel 2026-03-12 14:02:34 +01:00 committed by Manivannan Sadhasivam
parent 33642e9e36
commit 5a95fecbdd
5 changed files with 27 additions and 15 deletions
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12
drivers/pci/controller/dwc/pci-imx6.c
View File

@ -1433,19 +1433,19 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
static const struct pci_epc_features imx8m_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
.bar[BAR_1] = { .type = BAR_RESERVED, },
.bar[BAR_3] = { .type = BAR_RESERVED, },
.bar[BAR_1] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
.bar[BAR_5] = { .type = BAR_RESERVED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};
static const struct pci_epc_features imx8q_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
.bar[BAR_1] = { .type = BAR_RESERVED, },
.bar[BAR_3] = { .type = BAR_RESERVED, },
.bar[BAR_5] = { .type = BAR_RESERVED, },
.bar[BAR_1] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};

12
drivers/pci/controller/dwc/pci-keystone.c
View File

@ -933,6 +933,18 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
.msix_capable = true,
/*
* TODO: This driver is the only DWC glue driver that had BAR_RESERVED
* BARs, but did not call dw_pcie_ep_reset_bar() for the reserved BARs.
*
* To not change the existing behavior, these BARs were not migrated to
* BAR_DISABLED. If this driver wants the BAR_RESERVED BARs to be
* disabled, it should migrate them to BAR_DISABLED.
*
* If they actually should be enabled, then the driver must also define
* what is behind these reserved BARs, see the definition of struct
* pci_epc_bar_rsvd_region.
*/
.bar[BAR_0] = { .type = BAR_RESERVED, },
.bar[BAR_1] = { .type = BAR_RESERVED, },
.bar[BAR_2] = { .type = BAR_RESIZABLE, },

6
drivers/pci/controller/dwc/pcie-rcar-gen4.c
View File

@ -422,10 +422,10 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
.bar[BAR_1] = { .type = BAR_RESERVED, },
.bar[BAR_3] = { .type = BAR_RESERVED, },
.bar[BAR_1] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
.bar[BAR_5] = { .type = BAR_RESERVED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_1M,
};

8
drivers/pci/controller/dwc/pcie-tegra194.c
View File

@ -1993,10 +1993,10 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
.msi_capable = true,
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
.only_64bit = true, },
.bar[BAR_2] = { .type = BAR_RESERVED, },
.bar[BAR_3] = { .type = BAR_RESERVED, },
.bar[BAR_4] = { .type = BAR_RESERVED, },
.bar[BAR_5] = { .type = BAR_RESERVED, },
.bar[BAR_2] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_DISABLED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};

4
drivers/pci/controller/dwc/pcie-uniphier-ep.c
View File

@ -427,8 +427,8 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
.align = 1 << 16,
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_2] = { .only_64bit = true, },
.bar[BAR_4] = { .type = BAR_RESERVED, },
.bar[BAR_5] = { .type = BAR_RESERVED, },
.bar[BAR_4] = { .type = BAR_DISABLED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
},
};