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arm: dts: OMAP updates for v6.17

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- new board support: Seeed BeagleBone Green Eco
 - misc. fixups / cleanups
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Merge tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt

arm: dts: OMAP updates for v6.17
- new board support: Seeed BeagleBone Green Eco
- misc. fixups / cleanups

* tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
  arm: dts: ti: omap: Fixup pinheader typo
  ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching
  arm: dts: omap: Add support for BeagleBone Green Eco board
  dt-bindings: omap: Add Seeed BeagleBone Green Eco
  arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node
  Revert "ARM: dts: Update pcie ranges for dra7"
  ARM: dts: omap: am335x: Use non-deprecated rts-gpios

Link: https://lore.kernel.org/r/7h7c0gxczy.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-07-21 17:05:46 +02:00
commit 5a793f891a
8 changed files with 190 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/ti/omap.yaml
View File

@ -107,6 +107,7 @@ properties:
- compulab,cm-t335
- moxa,uc-8100-me-t
- novatech,am335x-lxm
- seeed,am335x-bone-green-eco
- ti,am335x-bone
- ti,am335x-evm
- ti,am3359-icev2

1
arch/arm/boot/dts/ti/omap/Makefile
View File

@ -93,6 +93,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-boneblue.dtb \
am335x-bonegreen.dtb \
am335x-bonegreen-wireless.dtb \
am335x-bonegreen-eco.dtb \
am335x-chiliboard.dtb \
am335x-cm-t335.dtb \
am335x-evm.dtb \

2
arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
View File

@ -212,7 +212,7 @@ &i2c0 {
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
tps: pmic@24 {
reg = <0x24>;
};

2
arch/arm/boot/dts/ti/omap/am335x-boneblack.dts
View File

@ -35,7 +35,7 @@ &gpio0 {
"P9_18 [spi0_d1]",
"P9_17 [spi0_cs0]",
"[mmc0_cd]",
"P8_42A [ecappwm0]",
"P9_42A [ecappwm0]",
"P8_35 [lcd d12]",
"P8_33 [lcd d13]",
"P8_31 [lcd d14]",

169
arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts Normal file
View File

@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2025 Bootlin
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-bonegreen-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "Seeed Studio BeagleBone Green Eco";
compatible = "seeed,am335x-bone-green-eco", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&buck1>;
};
};
sys_5v: regulator-sys-5v {
compatible = "regulator-fixed";
regulator-name = "sys_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
v3v3: regulator-v3v3 {
compatible = "regulator-fixed";
regulator-name = "v3v3";
regulator-always-on;
};
};
&usb0 {
interrupts-extended = <&intc 18>;
interrupt-names = "mc";
};
&baseboard_eeprom {
vcc-supply = <&v3v3>;
};
&i2c0 {
/delete-node/ pmic@24;
tps65214: pmic@30 {
compatible = "ti,tps65214";
reg = <0x30>;
buck1-supply = <&sys_5v>;
buck2-supply = <&sys_5v>;
buck3-supply = <&sys_5v>;
ldo1-supply = <&sys_5v>;
ldo2-supply = <&sys_5v>;
interrupt-parent = <&intc>;
interrupts = <7>;
pinctrl-0 = <&pmic_irq_pins_default>;
regulators {
buck1: buck1 {
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1298500>;
regulator-boot-on;
regulator-always-on;
};
buck2: buck2 {
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
buck3: buck3 {
regulator-name = "vdds_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "vdd_1v8_1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-name = "vdd_1v8_2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&cpsw_port1 {
phy-mode = "rgmii-id";
phy-handle = <&dp83867_0>;
ti,dual-emac-pvid = <1>;
};
&mac_sw {
pinctrl-0 = <&cpsw_b_default>;
pinctrl-1 = <&cpsw_b_sleep>;
};
&davinci_mdio_sw {
/delete-node/ ethernet-phy@0;
dp83867_0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
&am33xx_pinmux {
cpsw_b_default: cpsw-b-default-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)
>;
};
cpsw_b_sleep: cpsw-b-sleep-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(AM335X_PIN_NNMI, PIN_INPUT_PULLUP | MUX_MODE0)
>;
};
};

8
arch/arm/boot/dts/ti/omap/am335x-nano.dts
View File

@ -167,7 +167,7 @@ &uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <1 1>;
@ -178,7 +178,7 @@ &uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rts-delay = <1 1>;
linux,rs485-enabled-at-boot-time;
@ -187,7 +187,7 @@ &uart2 {
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <1 1>;
@ -198,7 +198,7 @@ &uart3 {
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <1 1>;

3
arch/arm/boot/dts/ti/omap/am335x-pdu001.dts
View File

@ -256,8 +256,9 @@ &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <0 0>;
linux,rs485-enabled-at-boot-time;

29
arch/arm/boot/dts/ti/omap/dra7.dtsi
View File

@ -195,24 +195,22 @@ axi0: target-module@51000000 {
clock-names = "fck", "phy-clk", "phy-clk-div";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000>,
<0x20000000 0x20000000 0x10000000>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
dma-ranges;
/**
* To enable PCI endpoint mode, disable the pcie1_rc
* node and enable pcie1_ep mode.
*/
pcie1_rc: pcie@51000000 {
reg = <0x51000000 0x2000>,
<0x51002000 0x14c>,
<0x20001000 0x2000>;
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
<0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -235,10 +233,7 @@ pcie1_intc: interrupt-controller {
};
pcie1_ep: pcie_ep@51000000 {
reg = <0x51000000 0x28>,
<0x51002000 0x14c>,
<0x51001000 0x28>,
<0x20001000 0x10000000>;
reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
interrupts = <0 232 0x4>;
num-lanes = <1>;
@ -269,21 +264,19 @@ axi1: target-module@51800000 {
reset-names = "rstctrl";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51800000 0x51800000 0x3000>,
<0x30000000 0x30000000 0x10000000>;
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
dma-ranges;
status = "disabled";
pcie2_rc: pcie@51800000 {
reg = <0x51800000 0x2000>,
<0x51802000 0x14c>,
<0x30001000 0x2000>;
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 355 0x4>, <0 356 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
<0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;