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scsi: ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

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Enable internal clock gating for Qualcomm UFS host controller by setting
the following attributes to 1 during host controller initialization:

 - DL_VS_CLK_CFG
 - PA_VS_CLK_CFG_REG
 - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN

This change is necessary to support the internal clock gating mechanism
in Qualcomm UFS host controller. This is power saving feature and hence
driver can continue to function correctly despite any error in enabling
these feature.

Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Link: https://lore.kernel.org/r/20250714075336.2133-4-quic_nitirawa@quicinc.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Nitin Rawat 2025-07-14 13:23:36 +05:30 committed by Martin K. Petersen
parent c49601642f
commit 5a6f304f39
2 changed files with 30 additions and 0 deletions
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21
drivers/ufs/host/ufs-qcom.c
View File

@ -552,11 +552,32 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
*/
static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
{
int err;
/* Enable UTP internal clock gating */
ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
REG_UFS_CFG2);
/* Ensure that HW clock gating is enabled before next operations */
ufshcd_readl(hba, REG_UFS_CFG2);
/* Enable Unipro internal clock gating */
err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK,
DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG);
if (err)
goto out;
err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK,
PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG);
if (err)
goto out;
err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
DME_VS_CORE_CLK_CTRL);
out:
if (err)
dev_err(hba->dev, "hw clk gating enabled failed\n");
}
static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,

9
drivers/ufs/host/ufs-qcom.h
View File

@ -24,6 +24,15 @@
#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
/* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */
#define PA_VS_CLK_CFG_REG 0x9004
#define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0)
/* bit and mask definitions for DL_VS_CLK_CFG attribute */
#define DL_VS_CLK_CFG 0xA00B
#define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9)
/* QCOM UFS host controller vendor specific registers */
enum {
REG_UFS_SYS1CLK_1US = 0xC0,