From 5a3dcad8e101ddcd3a886907c8992df54472f749 Mon Sep 17 00:00:00 2001 From: Daniel Machon Date: Tue, 20 Oct 2026 10:58:58 +0200 Subject: [PATCH] net: sparx5/lan969x: do not clobber the PSFP cycle timer update period sparx5_psfp_init() enables the periodic stream gate cycle timer update, which keeps the cycle start time of each stream gate within one cycle time of the current time. SG_CT_CLKS sets the update period, in system clock cycles. Before this patch, the update is enabled with a full register write of SG_CT_UPDATE_ENA only, which also sets SG_CT_CLKS to zero. That is below the documented minimum, the number of stream gates (1024 on sparx5 and 256 on lan969x). Write both fields, and set the period to the recommended 10 us, computed from the core clock since it differs per target (6250 cycles at 625 MHz, 3280 at 328 MHz). Found by an AI code review agent, and confirmed on lan969x and sparx5 by reading the register back as 0x80000000. Fixes: e116b19db202 ("net: microchip: sparx5: initialize PSFP") Signed-off-by: Daniel Machon Link: https://patch.msgid.link/20261020-sparx5-psfp-cycle-timer-v1-1-00f2908f096a@microchip.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c index 83b37f95ee46..fa19a48f941d 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c @@ -322,6 +322,7 @@ void sparx5_psfp_init(struct sparx5 *sparx5) { const struct sparx5_ops *ops = sparx5->data->ops; const struct sparx5_sdlb_group *group; + u32 sg_ct_clks; int i; for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { @@ -330,7 +331,14 @@ void sparx5_psfp_init(struct sparx5 *sparx5) group->min_burst, group->frame_size, i); } - spx5_wr(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(1), + /* Poll the stream gate cycle start times every 10 us. The core clock + * period is in picoseconds. + */ + sg_ct_clks = 10 * NSEC_PER_USEC * PSEC_PER_NSEC / + sparx5_clk_period(sparx5->coreclock); + + spx5_wr(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(sg_ct_clks) | + ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(1), sparx5, ANA_AC_SG_CYCLETIME_UPDATE_PERIOD); spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1),