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Merge branch 'pci/enumeration'
- Batch sizing of multiple BARs while memory decoding is disabled instead of disabling/enabling decoding for each BAR individually; this optimizes virtualized environments where toggling decoding enable is expensive (Alex Williamson) * pci/enumeration: PCI: Batch BAR sizing operations
This commit is contained in:
Bjorn Helgaas
commit
5a1d568ad1
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@ -747,6 +747,7 @@ static int sriov_init(struct pci_dev *dev, int pos)
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struct resource *res;
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const char *res_name;
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struct pci_dev *pdev;
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u32 sriovbars[PCI_SRIOV_NUM_BARS];
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pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
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if (ctrl & PCI_SRIOV_CTRL_VFE) {
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@ -783,6 +784,10 @@ static int sriov_init(struct pci_dev *dev, int pos)
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if (!iov)
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return -ENOMEM;
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/* Sizing SR-IOV BARs with VF Enable cleared - no decode */
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__pci_size_stdbars(dev, PCI_SRIOV_NUM_BARS,
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pos + PCI_SRIOV_BAR, sriovbars);
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nres = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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@ -796,7 +801,8 @@ static int sriov_init(struct pci_dev *dev, int pos)
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bar64 = (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
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else
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bar64 = __pci_read_base(dev, pci_bar_unknown, res,
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pos + PCI_SRIOV_BAR + i * 4);
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pos + PCI_SRIOV_BAR + i * 4,
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&sriovbars[i]);
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if (!res->flags)
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continue;
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if (resource_size(res) & (PAGE_SIZE - 1)) {
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@ -315,8 +315,10 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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void __pci_size_stdbars(struct pci_dev *dev, int count,
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unsigned int pos, u32 *sizes);
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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struct resource *res, unsigned int reg, u32 *sizes);
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void pci_configure_ari(struct pci_dev *dev);
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void __pci_bus_size_bridges(struct pci_bus *bus,
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struct list_head *realloc_head);
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@ -164,41 +164,67 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
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/**
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* __pci_size_bars - Read the raw BAR mask for a range of PCI BARs
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* @dev: the PCI device
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* @count: number of BARs to size
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* @pos: starting config space position
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* @sizes: array to store mask values
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* @rom: indicate whether to use ROM mask, which avoids enabling ROM BARs
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*
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* Provided @sizes array must be sufficiently sized to store results for
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* @count u32 BARs. Caller is responsible for disabling decode to specified
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* BAR range around calling this function. This function is intended to avoid
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* disabling decode around sizing each BAR individually, which can result in
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* non-trivial overhead in virtualized environments with very large PCI BARs.
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*/
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static void __pci_size_bars(struct pci_dev *dev, int count,
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unsigned int pos, u32 *sizes, bool rom)
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{
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u32 orig, mask = rom ? PCI_ROM_ADDRESS_MASK : ~0;
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int i;
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for (i = 0; i < count; i++, pos += 4, sizes++) {
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pci_read_config_dword(dev, pos, &orig);
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pci_write_config_dword(dev, pos, mask);
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pci_read_config_dword(dev, pos, sizes);
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pci_write_config_dword(dev, pos, orig);
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}
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}
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void __pci_size_stdbars(struct pci_dev *dev, int count,
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unsigned int pos, u32 *sizes)
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{
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__pci_size_bars(dev, count, pos, sizes, false);
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}
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static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes)
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{
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__pci_size_bars(dev, 1, pos, sizes, true);
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}
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/**
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* __pci_read_base - Read a PCI BAR
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* @dev: the PCI device
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* @type: type of the BAR
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* @res: resource buffer to be filled in
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* @pos: BAR position in the config space
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* @sizes: array of one or more pre-read BAR masks
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*
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* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
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*/
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int pos)
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struct resource *res, unsigned int pos, u32 *sizes)
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{
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u32 l = 0, sz = 0, mask;
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u32 l = 0, sz;
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u64 l64, sz64, mask64;
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u16 orig_cmd;
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struct pci_bus_region region, inverted_region;
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const char *res_name = pci_resource_name(dev, res - dev->resource);
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mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
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/* No printks while decoding is disabled! */
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if (!dev->mmio_always_on) {
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pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
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if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
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pci_write_config_word(dev, PCI_COMMAND,
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orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
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}
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}
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res->name = pci_name(dev);
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pci_read_config_dword(dev, pos, &l);
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pci_write_config_dword(dev, pos, l | mask);
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pci_read_config_dword(dev, pos, &sz);
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pci_write_config_dword(dev, pos, l);
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sz = sizes[0];
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/*
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* All bits set in sz means the device isn't working properly.
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@ -238,18 +264,13 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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if (res->flags & IORESOURCE_MEM_64) {
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pci_read_config_dword(dev, pos + 4, &l);
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pci_write_config_dword(dev, pos + 4, ~0);
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pci_read_config_dword(dev, pos + 4, &sz);
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pci_write_config_dword(dev, pos + 4, l);
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sz = sizes[1];
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l64 |= ((u64)l << 32);
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sz64 |= ((u64)sz << 32);
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mask64 |= ((u64)~0 << 32);
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}
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if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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if (!sz64)
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goto fail;
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@ -320,7 +341,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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u32 rombar, stdbars[PCI_STD_NUM_BARS];
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unsigned int pos, reg;
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u16 orig_cmd;
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BUILD_BUG_ON(howmany > PCI_STD_NUM_BARS);
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if (dev->non_compliant_bars)
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return;
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@ -329,10 +354,28 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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if (dev->is_virtfn)
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return;
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/* No printks while decoding is disabled! */
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if (!dev->mmio_always_on) {
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pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
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if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
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pci_write_config_word(dev, PCI_COMMAND,
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orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
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}
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}
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__pci_size_stdbars(dev, howmany, PCI_BASE_ADDRESS_0, stdbars);
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if (rom)
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__pci_size_rom(dev, rom, &rombar);
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if (!dev->mmio_always_on &&
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(orig_cmd & PCI_COMMAND_DECODE_ENABLE))
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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for (pos = 0; pos < howmany; pos++) {
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struct resource *res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
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pos += __pci_read_base(dev, pci_bar_unknown,
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res, reg, &stdbars[pos]);
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}
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if (rom) {
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@ -340,7 +383,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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dev->rom_base_reg = rom;
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
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__pci_read_base(dev, pci_bar_mem32, res, rom);
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__pci_read_base(dev, pci_bar_mem32, res, rom, &rombar);
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}
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}
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