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clk:ast2600 fix for hpll calculate

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Change-Id: I0043a785713881e93569d7bfbf384269fe9b294a
This commit is contained in:
Ryan Chen 2021-11-24 11:25:50 +08:00
parent 1bdfc7d909
commit 5a1b0e191a
1 changed files with 27 additions and 1 deletions
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28
drivers/clk/clk-ast2600.c
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@ -221,6 +221,32 @@ static const struct clk_div_table ast2600_div_table[] = {
};
/* For hpll/dpll/epll/mpll */
static struct clk_hw *ast2600_calc_hpll(const char *name, u32 val)
{
unsigned int mult, div;
u32 hwstrap = readl(scu_g6_base + ASPEED_G6_STRAP1);
if (val & BIT(24)) {
/* Pass through mode */
mult = div = 1;
} else {
/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
u32 m = val & 0x1fff;
u32 n = (val >> 13) & 0x3f;
u32 p = (val >> 19) & 0xf;
if (hwstrap & BIT(10))
m = 0x5F;
else if (hwstrap & BIT(8))
m = 0xBF;
mult = (m + 1) / (n + 1);
div = (p + 1);
}
return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
mult, div);
};
static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
{
unsigned int mult, div;
@ -774,7 +800,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
* and we assume that it is enabled
*/
regmap_read(map, ASPEED_HPLL_PARAM, &val);
aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_hpll("hpll", val);
regmap_read(map, ASPEED_MPLL_PARAM, &val);
aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);