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synced 2026-06-05 13:06:59 +02:00
ASoC: rt5677: Refactor GPIO and use
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: The code can be simplified with refactored GPIO parts and with use of device_get_match_data(). Besides that couple of additional changes, one for maintenance and one for making IRQ domain agnostic (not being pinned to OF).
This commit is contained in:
Mark Brown
commit
5a043fd5c7
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@ -6,23 +6,21 @@
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* Author: Oder Chiou <oder_chiou@realtek.com>
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*/
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#include <linux/acpi.h>
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#include <linux/fs.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/firmware.h>
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#include <linux/of_device.h>
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#include <linux/property.h>
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#include <linux/irq.h>
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#include <linux/fs.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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@ -4717,50 +4715,34 @@ static int rt5677_set_bias_level(struct snd_soc_component *component,
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return 0;
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}
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static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v)
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{
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unsigned int bank = offset / 5;
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unsigned int shift = (offset % 5) * 3;
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unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2;
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return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
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}
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#ifdef CONFIG_GPIOLIB
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static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
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int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO;
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int m = RT5677_GPIOx_OUT_MASK;
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switch (offset) {
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case RT5677_GPIO1 ... RT5677_GPIO5:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
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0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
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break;
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case RT5677_GPIO6:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
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RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
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break;
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default:
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break;
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}
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rt5677_update_gpio_bits(rt5677, offset, m, level);
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}
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static int rt5677_gpio_direction_out(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
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int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO;
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int m = RT5677_GPIOx_DIR_MASK | RT5677_GPIOx_OUT_MASK;
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int v = RT5677_GPIOx_DIR_OUT | level;
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switch (offset) {
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case RT5677_GPIO1 ... RT5677_GPIO5:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
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0x3 << (offset * 3 + 1),
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(0x2 | !!value) << (offset * 3 + 1));
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break;
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case RT5677_GPIO6:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
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RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
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RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
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break;
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default:
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break;
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}
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return 0;
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return rt5677_update_gpio_bits(rt5677, offset, m, v);
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}
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static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
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@ -4778,26 +4760,14 @@ static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
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static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
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{
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struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
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int m = RT5677_GPIOx_DIR_MASK;
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int v = RT5677_GPIOx_DIR_IN;
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switch (offset) {
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case RT5677_GPIO1 ... RT5677_GPIO5:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
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0x1 << (offset * 3 + 2), 0x0);
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break;
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case RT5677_GPIO6:
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
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RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
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break;
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default:
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break;
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}
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return 0;
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return rt5677_update_gpio_bits(rt5677, offset, m, v);
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}
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/** Configures the gpio as
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/*
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* Configures the GPIO as
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* 0 - floating
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* 1 - pull down
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* 2 - pull up
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@ -5539,7 +5509,7 @@ static int rt5677_init_irq(struct i2c_client *i2c)
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RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
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/* Ready to listen for interrupts */
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rt5677->domain = irq_domain_add_linear(i2c->dev.of_node,
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rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev),
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RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
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if (!rt5677->domain) {
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dev_err(&i2c->dev, "Failed to create IRQ domain\n");
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@ -5559,6 +5529,7 @@ static int rt5677_init_irq(struct i2c_client *i2c)
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static int rt5677_i2c_probe(struct i2c_client *i2c)
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{
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struct device *dev = &i2c->dev;
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struct rt5677_priv *rt5677;
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int ret;
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unsigned int val;
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@ -5573,21 +5544,9 @@ static int rt5677_i2c_probe(struct i2c_client *i2c)
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INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
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i2c_set_clientdata(i2c, rt5677);
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if (i2c->dev.of_node) {
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const struct of_device_id *match_id;
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match_id = of_match_device(rt5677_of_match, &i2c->dev);
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if (match_id)
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rt5677->type = (enum rt5677_type)match_id->data;
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} else if (ACPI_HANDLE(&i2c->dev)) {
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const struct acpi_device_id *acpi_id;
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acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
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if (acpi_id)
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rt5677->type = (enum rt5677_type)acpi_id->driver_data;
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} else {
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rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev);
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if (rt5677->type == 0)
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return -EINVAL;
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}
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rt5677_read_device_properties(rt5677, &i2c->dev);
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@ -5673,9 +5632,9 @@ static int rt5677_i2c_probe(struct i2c_client *i2c)
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regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
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RT5677_GPIO5_FUNC_MASK,
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RT5677_GPIO5_FUNC_DMIC);
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
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RT5677_GPIO5_DIR_MASK,
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RT5677_GPIO5_DIR_OUT);
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rt5677_update_gpio_bits(rt5677, RT5677_GPIO5,
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RT5677_GPIOx_DIR_MASK,
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RT5677_GPIOx_DIR_OUT);
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}
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if (rt5677->pdata.micbias1_vdd_3v3)
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@ -5702,7 +5661,7 @@ static struct i2c_driver rt5677_i2c_driver = {
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.driver = {
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.name = RT5677_DRV_NAME,
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.of_match_table = rt5677_of_match,
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.acpi_match_table = ACPI_PTR(rt5677_acpi_match),
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.acpi_match_table = rt5677_acpi_match,
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},
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.probe = rt5677_i2c_probe,
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.remove = rt5677_i2c_remove,
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@ -1587,81 +1587,19 @@
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#define RT5677_FUNC_MODE_DMIC_GPIO (0x0 << 13)
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#define RT5677_FUNC_MODE_JTAG (0x1 << 13)
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/* GPIO Control 2 (0xc1) */
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#define RT5677_GPIO5_DIR_MASK (0x1 << 14)
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#define RT5677_GPIO5_DIR_SFT 14
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#define RT5677_GPIO5_DIR_IN (0x0 << 14)
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#define RT5677_GPIO5_DIR_OUT (0x1 << 14)
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#define RT5677_GPIO5_OUT_MASK (0x1 << 13)
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#define RT5677_GPIO5_OUT_SFT 13
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#define RT5677_GPIO5_OUT_LO (0x0 << 13)
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#define RT5677_GPIO5_OUT_HI (0x1 << 13)
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#define RT5677_GPIO5_P_MASK (0x1 << 12)
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#define RT5677_GPIO5_P_SFT 12
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#define RT5677_GPIO5_P_NOR (0x0 << 12)
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#define RT5677_GPIO5_P_INV (0x1 << 12)
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#define RT5677_GPIO4_DIR_MASK (0x1 << 11)
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#define RT5677_GPIO4_DIR_SFT 11
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#define RT5677_GPIO4_DIR_IN (0x0 << 11)
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#define RT5677_GPIO4_DIR_OUT (0x1 << 11)
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#define RT5677_GPIO4_OUT_MASK (0x1 << 10)
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#define RT5677_GPIO4_OUT_SFT 10
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#define RT5677_GPIO4_OUT_LO (0x0 << 10)
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#define RT5677_GPIO4_OUT_HI (0x1 << 10)
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#define RT5677_GPIO4_P_MASK (0x1 << 9)
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#define RT5677_GPIO4_P_SFT 9
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#define RT5677_GPIO4_P_NOR (0x0 << 9)
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#define RT5677_GPIO4_P_INV (0x1 << 9)
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#define RT5677_GPIO3_DIR_MASK (0x1 << 8)
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#define RT5677_GPIO3_DIR_SFT 8
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#define RT5677_GPIO3_DIR_IN (0x0 << 8)
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#define RT5677_GPIO3_DIR_OUT (0x1 << 8)
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#define RT5677_GPIO3_OUT_MASK (0x1 << 7)
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#define RT5677_GPIO3_OUT_SFT 7
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#define RT5677_GPIO3_OUT_LO (0x0 << 7)
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#define RT5677_GPIO3_OUT_HI (0x1 << 7)
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#define RT5677_GPIO3_P_MASK (0x1 << 6)
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#define RT5677_GPIO3_P_SFT 6
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#define RT5677_GPIO3_P_NOR (0x0 << 6)
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#define RT5677_GPIO3_P_INV (0x1 << 6)
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#define RT5677_GPIO2_DIR_MASK (0x1 << 5)
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#define RT5677_GPIO2_DIR_SFT 5
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#define RT5677_GPIO2_DIR_IN (0x0 << 5)
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#define RT5677_GPIO2_DIR_OUT (0x1 << 5)
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#define RT5677_GPIO2_OUT_MASK (0x1 << 4)
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#define RT5677_GPIO2_OUT_SFT 4
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#define RT5677_GPIO2_OUT_LO (0x0 << 4)
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#define RT5677_GPIO2_OUT_HI (0x1 << 4)
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#define RT5677_GPIO2_P_MASK (0x1 << 3)
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#define RT5677_GPIO2_P_SFT 3
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#define RT5677_GPIO2_P_NOR (0x0 << 3)
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#define RT5677_GPIO2_P_INV (0x1 << 3)
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#define RT5677_GPIO1_DIR_MASK (0x1 << 2)
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#define RT5677_GPIO1_DIR_SFT 2
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#define RT5677_GPIO1_DIR_IN (0x0 << 2)
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#define RT5677_GPIO1_DIR_OUT (0x1 << 2)
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#define RT5677_GPIO1_OUT_MASK (0x1 << 1)
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#define RT5677_GPIO1_OUT_SFT 1
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#define RT5677_GPIO1_OUT_LO (0x0 << 1)
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#define RT5677_GPIO1_OUT_HI (0x1 << 1)
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#define RT5677_GPIO1_P_MASK (0x1 << 0)
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#define RT5677_GPIO1_P_SFT 0
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#define RT5677_GPIO1_P_NOR (0x0 << 0)
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#define RT5677_GPIO1_P_INV (0x1 << 0)
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/* GPIO Control 3 (0xc2) */
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#define RT5677_GPIO6_DIR_MASK (0x1 << 2)
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#define RT5677_GPIO6_DIR_SFT 2
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#define RT5677_GPIO6_DIR_IN (0x0 << 2)
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#define RT5677_GPIO6_DIR_OUT (0x1 << 2)
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#define RT5677_GPIO6_OUT_MASK (0x1 << 1)
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#define RT5677_GPIO6_OUT_SFT 1
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#define RT5677_GPIO6_OUT_LO (0x0 << 1)
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#define RT5677_GPIO6_OUT_HI (0x1 << 1)
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#define RT5677_GPIO6_P_MASK (0x1 << 0)
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#define RT5677_GPIO6_P_SFT 0
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#define RT5677_GPIO6_P_NOR (0x0 << 0)
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#define RT5677_GPIO6_P_INV (0x1 << 0)
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/* GPIO Control 2 (0xc1) & 3 (0xc2) common bits */
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#define RT5677_GPIOx_DIR_MASK (0x1 << 2)
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#define RT5677_GPIOx_DIR_SFT 2
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#define RT5677_GPIOx_DIR_IN (0x0 << 2)
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#define RT5677_GPIOx_DIR_OUT (0x1 << 2)
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#define RT5677_GPIOx_OUT_MASK (0x1 << 1)
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#define RT5677_GPIOx_OUT_SFT 1
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#define RT5677_GPIOx_OUT_LO (0x0 << 1)
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#define RT5677_GPIOx_OUT_HI (0x1 << 1)
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#define RT5677_GPIOx_P_MASK (0x1 << 0)
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#define RT5677_GPIOx_P_SFT 0
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#define RT5677_GPIOx_P_NOR (0x0 << 0)
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#define RT5677_GPIOx_P_INV (0x1 << 0)
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/* General Control (0xfa) */
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#define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3)
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@ -1753,8 +1691,8 @@ enum {
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};
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enum rt5677_type {
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RT5677,
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RT5676,
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RT5677 = 1,
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RT5676 = 2,
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};
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/* ASRC clock source selection */
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