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arm64: dts: Update cache properties for Arm Ltd platforms

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The DeviceTree Specification v0.3 specifies that the cache node
"compatible" and "cache-level" properties are required.

Cf. s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the properties
for unified cache is present ('cache-size', ...).

Update the relevant device trees nodes accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Pierre Gondois 2022-11-07 16:56:58 +01:00 committed by Sudeep Holla
parent c4a7b9b587
commit 59fb813f97
7 changed files with 10 additions and 0 deletions
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1
arch/arm64/boot/dts/arm/corstone1000.dtsi
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@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;

1
arch/arm64/boot/dts/arm/foundation-v8.dtsi
View File

@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

2
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

2
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

2
arch/arm64/boot/dts/arm/juno.dts
View File

@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

1
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View File

@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};