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drm/amd: Add DCN401 related register definitions

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Update register headers.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2024-03-26 14:41:52 -04:00 committed by Alex Deucher
parent 96557f785a
commit 59a0c03a50
9 changed files with 162669 additions and 0 deletions
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108
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
View File

@ -12855,6 +12855,24 @@
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0 0x3036
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1 0x3037
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2 0x3038
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3 0x3039
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -12985,6 +13003,24 @@
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3092
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3093
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3094
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3 0x3095
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -13115,6 +13151,24 @@
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30ee
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30ef
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f0
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f1
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f3
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f4
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2 0x30f5
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3 0x30f6
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -13245,6 +13299,24 @@
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314a
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1 0x314b
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2 0x314c
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3 0x314d
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0 0x314f
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1 0x3150
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2 0x3151
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3 0x3152
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -13375,6 +13447,24 @@
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0 0x31a6
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1 0x31a7
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2 0x31a8
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3 0x31a9
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0 0x31ab
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1 0x31ac
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2 0x31ad
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3 0x31ae
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -13504,6 +13594,24 @@
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0 0x3202
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1 0x3203
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2 0x3204
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3 0x3205
#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA0 0x3207
#define mmDSCC5_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA1 0x3208
#define mmDSCC5_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA2 0x3209
#define mmDSCC5_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC5_DSCC_TEST_DEBUG_DATA3 0x320a
#define mmDSCC5_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec

56
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
View File

@ -18948,6 +18948,15 @@
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM1_CM_TEST_DEBUG_INDEX
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM1_CM_TEST_DEBUG_DATA
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
//DC_PERFMON13_PERFCOUNTER_CNTL
@ -21142,6 +21151,15 @@
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM2_CM_TEST_DEBUG_INDEX
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM2_CM_TEST_DEBUG_DATA
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
//DC_PERFMON14_PERFCOUNTER_CNTL
@ -23337,6 +23355,15 @@
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM3_CM_TEST_DEBUG_INDEX
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM3_CM_TEST_DEBUG_DATA
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
//DC_PERFMON15_PERFCOUNTER_CNTL
@ -25531,6 +25558,15 @@
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM4_CM_TEST_DEBUG_INDEX
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM4_CM_TEST_DEBUG_DATA
#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
//DC_PERFMON16_PERFCOUNTER_CNTL
@ -27726,6 +27762,15 @@
#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM5_CM_TEST_DEBUG_INDEX
#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM5_CM_TEST_DEBUG_DATA
#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
//DC_PERFMON17_PERFCOUNTER_CNTL
@ -50290,7 +50335,9 @@
#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
//DSC_TOP0_DSC_DEBUG_CONTROL
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
@ -50662,6 +50709,15 @@
//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec

90
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
View File

@ -11691,6 +11691,24 @@
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0 0x3036
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1 0x3037
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2 0x3038
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3 0x3039
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -11821,6 +11839,24 @@
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3092
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3093
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3094
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3 0x3095
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -11951,6 +11987,24 @@
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30ee
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30ef
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f0
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f1
#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f3
#define mmDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f4
#define mmDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2 0x30f5
#define mmDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3 0x30f6
#define mmDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -12081,6 +12135,24 @@
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314a
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1 0x314b
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2 0x314c
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3 0x314d
#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0 0x314f
#define mmDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1 0x3150
#define mmDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2 0x3151
#define mmDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3 0x3152
#define mmDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -12211,6 +12283,24 @@
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0 0x31a6
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1 0x31a7
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2 0x31a8
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3 0x31a9
#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0 0x31ab
#define mmDSCC4_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1 0x31ac
#define mmDSCC4_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2 0x31ad
#define mmDSCC4_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3 0x31ae
#define mmDSCC4_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec

44
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
View File

@ -17884,6 +17884,14 @@
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM1_CM_TEST_DEBUG_INDEX
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM1_CM_TEST_DEBUG_DATA
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@ -20084,6 +20092,14 @@
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM2_CM_TEST_DEBUG_INDEX
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM2_CM_TEST_DEBUG_DATA
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@ -22284,6 +22300,14 @@
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM3_CM_TEST_DEBUG_INDEX
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM3_CM_TEST_DEBUG_DATA
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@ -24484,6 +24508,14 @@
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM4_CM_TEST_DEBUG_INDEX
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM4_CM_TEST_DEBUG_DATA
#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@ -43650,7 +43682,9 @@
#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
//DSC_TOP0_DSC_DEBUG_CONTROL
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
@ -44023,6 +44057,15 @@
//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
@ -44173,6 +44216,7 @@
#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
//DSC_TOP1_DSC_DEBUG_CONTROL
#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L

16
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h
View File

@ -5695,6 +5695,14 @@
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0 0x3036
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1 0x3037
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2 0x3038
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3 0x3039
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b
@ -5835,6 +5843,14 @@
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3092
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3093
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3094
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3 0x3095
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097

16
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
View File

@ -11166,6 +11166,14 @@
#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM0_CM_TEST_DEBUG_INDEX
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM0_CM_TEST_DEBUG_DATA
#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@ -13366,6 +13374,14 @@
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
//CM1_CM_TEST_DEBUG_INDEX
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM1_CM_TEST_DEBUG_DATA
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec

28
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
View File

@ -11549,6 +11549,9 @@
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM0_CM_TEST_DEBUG_DATA
#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
@ -12683,6 +12686,14 @@
#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L
#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
//CM1_CM_TEST_DEBUG_INDEX
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM1_CM_TEST_DEBUG_DATA
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
@ -13817,6 +13828,14 @@
#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L
#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
//CM2_CM_TEST_DEBUG_INDEX
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM2_CM_TEST_DEBUG_DATA
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
@ -14951,6 +14970,14 @@
#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L
#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
//CM3_CM_TEST_DEBUG_INDEX
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//CM3_CM_TEST_DEBUG_DATA
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
@ -42328,6 +42355,7 @@
//DSC_TOP0_DSC_DEBUG_CONTROL
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec

16569
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h Normal file
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145742
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h Normal file
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