From c3ae1484e112343dc5d9fc33ca0cc83c994939c1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:11 +0530 Subject: [PATCH 1/9] ARM: dts: rockchip: Add SFC node to rv1126 Add Rockchip SFC controller node for rv1126. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-7-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 1f07d0a4fa73..0d1df3a8eb44 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -419,6 +419,18 @@ sdio: mmc@ffc70000 { status = "disabled"; }; + sfc: spi@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = ; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + clock-names = "clk_sfc", "hclk_sfc"; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; From d91d25b1db47fd5d91782298ac6e6e418aa2da46 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:12 +0530 Subject: [PATCH 2/9] ARM: dts: rockchip: Add rv1126 FSPI pins Add fspi pins for rv1126 sfc controller. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-8-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index b77021772781..dd470346b388 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -59,6 +59,24 @@ emmc_cmd: emmc-cmd { <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; }; }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_down>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_up>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_up>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_up>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_up>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_up>; + }; + }; i2c0 { /omit-if-no-ref/ i2c0_xfer: i2c0-xfer { From 753c8a7d8bbda86811943b62f8d33c2e0d5e7046 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:13 +0530 Subject: [PATCH 3/9] ARM: dts: rockchip: Add rv1126 uart5m2_xfer pins Add uart5m2_xfer pins for Rockchip RV1126 uart5. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-9-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index dd470346b388..554353e0a758 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -267,5 +267,13 @@ uart5m0_xfer: uart5m0-xfer { /* uart5_tx_m0 */ <3 RK_PA6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; }; }; From 012f90c31babdbd94f3e7bc80400f3d4ae5035bf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:15 +0530 Subject: [PATCH 4/9] ARM: dts: rockchip: Drop EMMC_RSTN for edgeble-neu2 EMMC_RSTN GPIO1_A3 is connected to FSPI_CLK in Edgeble Neu2 board. So, drop the same GPIO pin from eMMC. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-11-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi index cc64ba4be344..e3e5752fd6b7 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi @@ -52,7 +52,7 @@ &emmc { bus-width = <8>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; rockchip,default-sample-phase = <90>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vccio_flash>; From f544630dc4967fc58cc995d0d2dd3940d9848c39 Mon Sep 17 00:00:00 2001 From: Stephen Chen Date: Mon, 31 Jul 2023 16:05:16 +0530 Subject: [PATCH 5/9] ARM: dts: rockchip: Enable SFC for edgeble-neu2 Enable on module SPI Flash present in Edgeble Neu2. Tested-by: Jagan Teki Signed-off-by: Stephen Chen Link: https://lore.kernel.org/r/20230731103518.2906147-12-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rv1126-edgeble-neu2.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi index e3e5752fd6b7..6bbaf6da6545 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi @@ -301,6 +301,22 @@ &saradc { status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; From 5d1d164da4df3c744cf32cb1dae9fcd5837a0240 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:17 +0530 Subject: [PATCH 6/9] ARM: dts: rockchip: Add 3V3_SYS regulator for edgeble-neu2 Edgeble Neu2 IO board has 3V3_SYS regulator to power Audio, RS485, and 4G Module. Add regulator for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-13-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 3340fc3f0739..6dfcd7ff96ea 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -20,6 +20,16 @@ aliases { chosen { stdout-path = "serial2:1500000n8"; }; + + v3v3_sys: v3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; }; &gmac { From c991ed9f57c8025b248e284545c5310e67dc44cf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:18 +0530 Subject: [PATCH 7/9] ARM: dts: rockchip: Add 12V main supply for edgeble-neu2 The Main supply volatge for Edgeble Neu2 IO board is 12V DC. Add the 12v supply regulator for it and input to vcc5v0_sys. Since the power regulator is part of IO board circuit, move the regulator in IO dts file. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-14-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rv1126-edgeble-neu2-io.dts | 19 +++++++++++++++++++ .../dts/rockchip/rv1126-edgeble-neu2.dtsi | 9 --------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 6dfcd7ff96ea..3d587602e13a 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -21,6 +21,25 @@ chosen { stdout-path = "serial2:1500000n8"; }; + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + v3v3_sys: v3v3-sys-regulator { compatible = "regulator-fixed"; regulator-name = "v3v3_sys"; diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi index 6bbaf6da6545..7ea8d7d16f5f 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi @@ -11,15 +11,6 @@ aliases { mmc0 = &emmc; }; - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vccio_flash: vccio-flash-regulator { compatible = "regulator-fixed"; enable-active-high; From 4fafaed5afcc3a58e982629dbc0471ba9ba8678f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:30:07 +0530 Subject: [PATCH 8/9] ARM: dts: rockchip: Add rv1126 PD_VO entry PD_VO power-domain tree diagram in RV1126 is connected to - BIU_VO - VOP - RGA - IEP - DSIHOST Add PD_VO power-domain entry in RV1126. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731110012.2913742-10-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126.dtsi | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 0d1df3a8eb44..3efeec97cabc 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -125,6 +125,26 @@ qos_sdio: qos@fe86c000 { reg = <0xfe86c000 0x20>; }; + qos_iep: qos@fe8a0000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0000 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0080 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0100 0x20>; + }; + + qos_vop: qos@fe8a0180 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0180 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -170,6 +190,25 @@ power-domain@RV1126_PD_SDIO { pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; + + power-domain@RV1126_PD_VO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_vop>, + <&qos_iep>; + #power-domain-cells = <0>; + }; }; }; From 1bf0dcb1e2a987a9281ae91f94e10c0de52c4952 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:30:08 +0530 Subject: [PATCH 9/9] ARM: dts: rockchip: Add rv1126 VOP_LITE support RV1126 VOP_LITE supports the video output processing ofMIPI DSI, RGB display interfaces with max output resolution of 1920x1080. Add support for vop in rv1126. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731110012.2913742-11-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126.dtsi | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 3efeec97cabc..9c918420ecd5 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -83,6 +83,11 @@ timer { clock-frequency = <24000000>; }; + display_subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -371,6 +376,43 @@ timer0: timer@ff660000 { clock-names = "pclk", "timer"; }; + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + interrupts = ; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + reset-names = "axi", "ahb", "dclk"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + iommus = <&vop_mmu>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + #iommu-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + }; + gmac: ethernet@ffc40000 { compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; reg = <0xffc40000 0x4000>;