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wifi: rtw89: 8851b: rfk: update IQK to 0x14
Update IQK along with TX/RX clock to 960MHz and 1920MHz to improve performance. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20250627035338.16637-1-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
parent
56624544c8
commit
58f1510a8b
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@ -19,7 +19,7 @@
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#define RTW8851B_RXK_GROUP_NR 4
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#define RTW8851B_RXK_GROUP_IDX_NR 2
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#define RTW8851B_TXK_GROUP_NR 1
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#define RTW8851B_IQK_VER 0x2a
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#define RTW8851B_IQK_VER 0x14
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#define RTW8851B_IQK_SS 1
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#define RTW8851B_LOK_GRAM 10
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#define RTW8851B_TSSI_PATH_NR 1
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@ -1107,10 +1107,43 @@ static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
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rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
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if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80)
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if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
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rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
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rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
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_rxck_force(rtwdev, path, true, ADC_960M);
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rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_80_defs_tbl);
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else
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} else {
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rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
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rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
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_rxck_force(rtwdev, path, true, ADC_960M);
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rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_others_defs_tbl);
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}
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, (2)before RXK IQK\n", path);
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[07:10] = 0x%x\n", path,
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0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(10, 7)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[11:14] = 0x%x\n", path,
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0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(14, 11)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[26:27] = 0x%x\n", path,
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0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(27, 26)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[05:08] = 0x%x\n", path,
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0xc0d8, rtw89_phy_read32_mask(rtwdev, 0xc0d8, GENMASK(8, 5)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[17:21] = 0x%x\n", path,
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0xc0c4, rtw89_phy_read32_mask(rtwdev, 0xc0c4, GENMASK(21, 17)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[16:31] = 0x%x\n", path,
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0xc0e8, rtw89_phy_read32_mask(rtwdev, 0xc0e8, GENMASK(31, 16)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[04:05] = 0x%x\n", path,
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0xc0e4, rtw89_phy_read32_mask(rtwdev, 0xc0e4, GENMASK(5, 4)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[23:31] = 0x%x\n", path,
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0x12a0, rtw89_phy_read32_mask(rtwdev, 0x12a0, GENMASK(31, 23)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[13:14] = 0x%x\n", path,
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0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(14, 13)));
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[16:23] = 0x%x\n", path,
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0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(23, 16)));
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}
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static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev,
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@ -1616,6 +1649,14 @@ static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
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rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_macbb_defs_tbl);
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_txck_force(rtwdev, path, true, DAC_960M);
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rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
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_rxck_force(rtwdev, path, true, ADC_1920M);
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rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_macbb_bh_defs_tbl);
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}
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static void _iqk_init(struct rtw89_dev *rtwdev)
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@ -63,16 +63,7 @@ static const struct rtw89_reg5_def rtw8851b_dack_manual_off_defs[] = {
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RTW89_DECLARE_RFK_TBL(rtw8851b_dack_manual_off_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_80_defs[] = {
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RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0101),
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RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x2),
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RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x1),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x8),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x2),
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RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x2),
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RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x5),
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RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xf),
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RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0),
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RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f),
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@ -85,16 +76,7 @@ static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_80_defs[] = {
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_rxclk_80_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_others_defs[] = {
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RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0101),
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RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x2),
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RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x0),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x8),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x2),
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RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x2),
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RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x5),
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RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xf),
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RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x2),
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RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f),
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@ -157,30 +139,38 @@ static const struct rtw89_reg5_def rtw8851b_iqk_macbb_defs[] = {
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RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0),
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RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0xf801fffd),
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RTW89_DECL_RFK_WM(0x5670, 0x00004000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00008000, 0x1),
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RTW89_DECL_RFK_WM(0x5670, 0x80000000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00007000, 0x7),
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RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1),
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RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x3),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_macbb_bh_defs[] = {
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RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x2),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x9),
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RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x1),
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RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x0),
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RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x3),
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RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xa),
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RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0),
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RTW89_DECL_RFK_WM(0xc0e8, 0x00000040, 0x1),
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RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x1f),
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RTW89_DECL_RFK_DELAY(10),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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RTW89_DECL_RFK_DELAY(10),
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RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x1f),
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RTW89_DECL_RFK_DELAY(10),
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RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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RTW89_DECL_RFK_DELAY(2),
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RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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RTW89_DECL_RFK_DELAY(10),
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RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x1),
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RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_defs);
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_bh_defs);
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static const struct rtw89_reg5_def rtw8851b_tssi_sys_defs[] = {
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RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0xb5b5),
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@ -18,6 +18,7 @@ extern const struct rtw89_rfk_tbl rtw8851b_iqk_txk_2ghz_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_iqk_txk_5ghz_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_iqk_afebb_restore_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_iqk_macbb_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_iqk_macbb_bh_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_tssi_sys_defs_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_tssi_sys_a_defs_2g_tbl;
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extern const struct rtw89_rfk_tbl rtw8851b_tssi_sys_a_defs_5g_tbl;
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