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drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock

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[Why & How]
this is to force ODM 2:1 on single eDP to lower dispclk/dppclk.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2026-04-30 17:24:38 -04:00 committed by Alex Deucher
parent e13d718162
commit 58deba8c80
4 changed files with 28 additions and 1 deletions
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1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1219,6 +1219,7 @@ struct dc_debug_options {
unsigned int force_vmin_threshold;
bool enable_otg_frame_sync_pwa;
unsigned int min_deep_sleep_dcfclk_khz;
unsigned int force_odm2to1_for_edp_pixclk_mhz;
};

4
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
View File

@ -765,6 +765,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_deep_sleep_dcfclk_khz = 8000,
.replay_skip_crtc_disabled = true,
.psr_skip_crtc_disable = true,
.force_odm2to1_for_edp_pixclk_mhz = 550, // Force ODM 2to1 for eDP when pixel clock is above 550MHz
};
static const struct dc_check_config config_defaults = {
@ -1721,9 +1722,12 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc,
DC_FP_START();
dcn42_decide_odm_override(dc, context);
out = dml2_validate(dc, context, context->bw_ctx.dml2,
validate_mode);
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
/*not required for mode enumeration*/
dcn42_decide_zstate_support(dc, context);

22
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
View File

@ -45,3 +45,25 @@ void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context)
context->bw_ctx.bw.dcn.clk.zstate_support = support;
}
bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context)
{
bool odm_override = false;
DC_LOGGER_INIT(dc->ctx->logger);
if (dc->ctx->dce_environment == DCE_ENV_DIAG)
return false;
if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 &&
context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) {
odm_override = true;
context->streams[0]->debug.force_odm_combine_segments = 2;
}
DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n",
odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz);
}
return odm_override;
}

2
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h
View File

@ -29,5 +29,5 @@
#include "core_types.h"
void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context);
bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context);
#endif /* _DCN42_RESOURCE_FPU_H_ */