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enetc: Increase eMDIO MDC rate to 2.5 MHz

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The current eMDIO MDC rate is 558 kHz on i.MX95 B0. This is very low,
but also very compatible. However, for example NXP TJA1120 PHY needs
at minimum 1 MHz MDC clock and 558 kHz does not work with that PHY.

As a minimum change, increase the MDC clock to 2.5 MHz which matches
the 802.3 specification. Also, even old PHYs like LAN8210Ai, KSZ8794,
DP83822 support up to 2.5 MHz MDC clock frequency, and it covers the
NXP TJA1120 as well. There is no known rationale for why the 558 kHz
was picked when the eMDIO driver was added.

Signed-off-by: Marek Vasut <marex@nabladev.com>
Link: https://patch.msgid.link/20260924180607.60932-1-marex@nabladev.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Marek Vasut 2026-09-24 20:05:19 +02:00 committed by Jakub Kicinski
parent 0737138c55
commit 587acb86d6
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/freescale/enetc/enetc_mdio.c
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@ -24,7 +24,7 @@
#define ENETC_EMDIO_CFG \
(MDIO_CFG_HOLD(2) | \
MDIO_CFG_CLKDIV(258) | \
MDIO_CFG_CLKDIV(66) | \
MDIO_CFG_NEG)
#define MDIO_CTL_DEV_ADDR(x) ((x) & 0x1f)