From 400915493f53b10085648b387cdbb4da5612ebfc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:14 +0200 Subject: [PATCH 1/3] dt-bindings: Add Actiontec vendor prefix Actiontec is a US manufacturer of telecom equipment. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-1-cc804884474d@linaro.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..a0abe9e39291 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -48,6 +48,8 @@ patternProperties: description: Acme Systems srl "^actions,.*": description: Actions Semiconductor Co., Ltd. + "^actiontec,.*": + description: Actiontec Electronics, Inc "^active-semi,.*": description: Active-Semi International Inc "^ad,.*": From 873c5c0a2baf11d7101df3fc7485a0183c8c6c29 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:15 +0200 Subject: [PATCH 2/3] dt-bindings: arm: ixp4xx: List actiontec devices Add two IXP4xx device families from OpenWrts backlog: Actiontec MI424WR revision A/C and revision D, both of these are IXP4xx devices. Revisions E and later use different chipsets. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-2-cc804884474d@linaro.org --- Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d60792b1d995..b7b430896596 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -16,6 +16,8 @@ properties: oneOf: - items: - enum: + - actiontec,mi424wr-ac + - actiontec,mi424wr-d - adieng,coyote - arcom,vulcan - dlink,dsm-g600-a From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:16 +0200 Subject: [PATCH 3/3] ARM: dts: Add ixp4xx Actiontec MI424WR device trees The Actiontex MI424WR is a pretty widespread home router, made in many different revisions. Revisions A, C and D are based on IXP42x. We add a device tree for the A/C variant and one for the D variant as these differ in the location of the WAN PHY on the MDIO bus, and the ethernet interfaces for the WAN PHY and the DSA switch are switched around. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org --- arch/arm/boot/dts/intel/ixp/Makefile | 2 + .../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++ .../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++ .../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++ 4 files changed, 349 insertions(+) create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile index ab8525f1ea1d..cb30d8d55016 100644 --- a/arch/arm/boot/dts/intel/ixp/Makefile +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp42x-actiontec-mi424wr-ac.dtb \ + intel-ixp42x-actiontec-mi424wr-d.dtb \ intel-ixp42x-linksys-nslu2.dtb \ intel-ixp42x-linksys-wrv54g.dtb \ intel-ixp42x-freecom-fsg-3.dtb \ diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts new file mode 100644 index 000000000000..413b9255f9e3 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +/dts-v1/; + +#include "intel-ixp42x-actiontec-mi424wr.dtsi" + +/ { + model = "Actiontec MI424WR rev A/C"; + compatible = "actiontec,mi424wr-ac", "intel,ixp42x"; + + soc { + /* EthB used for WAN */ + ethernet@c8009000 { + phy-handle = <&phy17>; // 17 on revision A-C + + mdio { + phy17: ethernet-phy@17 { + /* WAN */ + reg = <17>; + }; + }; + }; + + /* EthC used for LAN */ + ethernet@c800a000 { + /* Fixed link to the CPU MII port on the KS8995 */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts new file mode 100644 index 000000000000..3619c6411a5c --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR revision D + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +/dts-v1/; + +#include "intel-ixp42x-actiontec-mi424wr.dtsi" + +/ { + model = "Actiontec MI424WR rev D"; + compatible = "actiontec,mi424wr-d", "intel,ixp42x"; + + soc { + /* EthB used for LAN */ + ethernet@c8009000 { + /* Fixed link to the CPU MII port on the KS8995 */ + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + /* PHY ID 0x00221450 */ + phy5: ethernet-phy@5 { + /* WAN */ + reg = <5>; + }; + }; + }; + + /* EthC used for WAN */ + ethernet@c800a000 { + phy-handle = <&phy5>; // 5 on revision D + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi new file mode 100644 index 000000000000..76fd97c5beb6 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +#include "intel-ixp42x.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-wan-coax { + color = ; + function = "wan-coax"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-power-alarm { + color = ; + function = LED_FUNCTION_ALARM; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-wireless { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-internet-down { + color = ; + function = "internet-down"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-internet-up { + color = ; + function = "internet-up"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-lan-coax { + color = ; + function = "lan-coax"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-wan-ethernet-alarm { + color = ; + function = "wan-ethernet-alarm"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + /* The last three LEDs are not mounted but traces exist on the PCB */ + led-phone-1 { + color = ; + function = "phone-1"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-phone-2 { + color = ; + function = "phone-2"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-voip { + color = ; + function = "voip"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + ethernet-switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + spi-max-frequency = <50000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&phy1>; + }; + ethernet-port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "mii"; + phy-handle = <&phy2>; + }; + ethernet-port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "mii"; + phy-handle = <&phy3>; + }; + ethernet-port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "mii"; + phy-handle = <&phy4>; + }; + ethernet-port@4 { + reg = <4>; + ethernet = <ðc>; + phy-mode = "mii"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + }; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x0800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + fis-index-block = <0x3f>; + }; + }; + gpio1: gpio@1,0 { + /* MMIO GPIO at CS1 */ + compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; + gpio-controller; + #gpio-cells = <2>; + big-endian; + reg = <1 0x00000000 0x2>; + reg-names = "dat"; + /* Expansion bus settings */ + intel,ixp4xx-eb-write-enable = <1>; + + pci-reset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCI reset"; + }; + pstn-relay-hog-1 { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PSTN relay control 1"; + }; + pstn-relay-hog-2 { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PSTN relay control 2"; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 13 */ + <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */ + <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */ + /* IDSEL 14 */ + <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ + <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */ + /* IDSEL 15 */ + <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */ + <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */ + }; + + ethb: ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "mii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* 1, 2, 3 and 4 are ports on the KS8995 switch */ + phy1: ethernet-phy@1 { + /* LAN1 */ + reg = <1>; + }; + phy2: ethernet-phy@2 { + /* LAN2 */ + reg = <2>; + }; + phy3: ethernet-phy@3 { + /* LAN3 */ + reg = <3>; + }; + phy4: ethernet-phy@4 { + /* LAN4 */ + reg = <4>; + }; + }; + }; + + ethc: ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "mii"; + }; + }; +};