github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-27 01:32:21 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Fix underrun regressions on Panther Lake by reverting the recent

Browse Source 
SCL=0 enablement for always-on VRR timing. It also includes a fix
 display LT PHY SSC programming and a small set of i915 fixes
 addressing NULL pointer dereferences, memory leaks and bound checks.
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmpPsRMACgkQ+mJfZA7r
 E8ppSAf/S65MM4nKWLP/c8SScFPaQzvynzmgcoj3z13pMb0IYZs9NlFysL1Ebi2T
 hm5Nai/e/2Jzh15+GL9xnJqY2c6Cv4A+P5803wSvsDUU2G+y8/EmY3qlqbxfKwcf
 KEnHyRuSYHL/dl0F+SLtTr7tgWNEYbAqnDNz6vY/hKPheJPxBHyVCZNharND907r
 1AJksf2NkbzOLBCnAP5tV4s29qqjO7jxKUp7LVsKD0Kha05Fwr+qgZjUluN8JtbJ
 vGmzhO7nO1/0D+3GSaRHXLcOd+V3ohJ2DkJnYbBe79NgYaKx3gW7oMNO2ZTLhFps
 Z0vAVmzGFltIUalZoClJ5+0Kek74MQ==
 =LSq3
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-fixes-2026-07-09' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes

Fix underrun regressions on Panther Lake by reverting the recent
SCL=0 enablement for always-on VRR timing. It also includes a fix
display LT PHY SSC programming and a small set of i915 fixes
addressing NULL pointer dereferences, memory leaks and bound checks.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/ak-xZPqluaXVJGtP@intel.com
This commit is contained in:
Dave Airlie 2026-07-10 12:27:02 +10:00
commit 58570ef9dc
5 changed files with 33 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -5737,8 +5737,9 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
struct intel_display *display = to_intel_display(intel_dp);
bool force_retrain = intel_dp->link.force_retrain;
bool reprobe_needed = false;
int tries = 33;
for (;;) {
while (--tries) {
u8 esi[4] = {};
u8 ack[4] = {};
bool new_irqs;
@ -5781,6 +5782,11 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
break;
}
if (!tries) {
drm_dbg_kms(display->drm, "DPRX ESI not clearing, device may be stuck\n");
reprobe_needed = true;
}
return !reprobe_needed;
}

6
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -1223,11 +1223,7 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
/* DP2.0 10G and 20G rates enable MPLLA*/
if (port_clock == 1000000 || port_clock == 2000000)
val |= XELPDP_SSC_ENABLE_PLLA;
else
val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |

3
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -1522,9 +1522,6 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
needs_panel_replay)
return 0;
if (intel_vrr_always_use_vrr_tg(display))
return 0;
return 1;
}

24
drivers/gpu/drm/i915/gem/i915_gem_context.c
View File

@ -769,8 +769,8 @@ static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
struct intel_engine_cs *engine;
if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
kfree(set.engines);
return -EFAULT;
err = -EFAULT;
goto err;
}
memset(&set.engines[n], 0, sizeof(set.engines[n]));
@ -786,8 +786,8 @@ static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
drm_dbg(&i915->drm,
"Invalid engine[%d]: { class:%d, instance:%d }\n",
n, ci.engine_class, ci.engine_instance);
kfree(set.engines);
return -ENOENT;
err = -ENOENT;
goto err;
}
set.engines[n].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
@ -800,15 +800,21 @@ static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
set_proto_ctx_engines_extensions,
ARRAY_SIZE(set_proto_ctx_engines_extensions),
&set);
if (err) {
kfree(set.engines);
return err;
}
if (err)
goto err_extensions;
pc->num_user_engines = set.num_engines;
pc->user_engines = set.engines;
return 0;
err_extensions:
for (n = 0; n < set.num_engines; n++)
kfree(set.engines[n].siblings);
err:
kfree(set.engines);
return err;
}
static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
@ -850,7 +856,7 @@ static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
pe = &pc->user_engines[idx];
/* Only render engine supports RPCS configuration. */
if (pe->engine->class != RENDER_CLASS)
if (!pe->engine || pe->engine->class != RENDER_CLASS)
return -EINVAL;
sseu = &pe->sseu;

19
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
View File

@ -3932,11 +3932,11 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
struct drm_i915_private *i915 = siblings[0]->i915;
struct virtual_engine *ve;
unsigned int n;
int err;
int err = -ENOMEM;
ve = kzalloc_flex(*ve, siblings, count);
if (!ve)
return ERR_PTR(-ENOMEM);
goto err;
ve->base.i915 = i915;
ve->base.gt = siblings[0]->gt;
@ -3968,10 +3968,8 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
intel_engine_init_execlists(&ve->base);
ve->base.sched_engine = i915_sched_engine_create(ENGINE_VIRTUAL);
if (!ve->base.sched_engine) {
err = -ENOMEM;
goto err_put;
}
if (!ve->base.sched_engine)
goto err_noput;
ve->base.sched_engine->private_data = &ve->base;
ve->base.cops = &virtual_context_ops;
@ -3987,10 +3985,8 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
intel_context_init(&ve->context, &ve->base);
ve->base.breadcrumbs = intel_breadcrumbs_create(NULL);
if (!ve->base.breadcrumbs) {
err = -ENOMEM;
if (!ve->base.breadcrumbs)
goto err_put;
}
for (n = 0; n < count; n++) {
struct intel_engine_cs *sibling = siblings[n];
@ -4065,8 +4061,13 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
virtual_engine_initial_hint(ve);
return &ve->context;
err_noput:
kfree(ve);
goto err;
err_put:
intel_context_put(&ve->context);
err:
return ERR_PTR(err);
}