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drm/amdgpu/vcn4.0.3: split code along instances
Split the code on a per instance basis. This will allow us to use the per instance functions in the future to handle more things per instance. v2: squash in fix for stop() from Boyuan Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
f4cd7a85db
commit
5826d5a5d5
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@ -1117,172 +1117,169 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
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* vcn_v4_0_3_start - VCN start
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*
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* @adev: amdgpu_device pointer
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* @i: instance to start
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*
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* Start VCN block
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*/
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static int vcn_v4_0_3_start(struct amdgpu_device *adev)
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static int vcn_v4_0_3_start(struct amdgpu_device *adev, int i)
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{
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volatile struct amdgpu_vcn4_fw_shared *fw_shared;
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struct amdgpu_ring *ring;
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int i, j, k, r, vcn_inst;
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int j, k, r, vcn_inst;
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uint32_t tmp;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
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r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
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continue;
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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return vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
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vcn_inst = GET_INST(VCN, i);
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/* set VCN status busy */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
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UVD_STATUS__UVD_BUSY;
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WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
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vcn_inst = GET_INST(VCN, i);
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/* set VCN status busy */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
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UVD_STATUS__UVD_BUSY;
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WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
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/*SW clock gating */
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vcn_v4_0_3_disable_clock_gating(adev, i);
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/* SW clock gating */
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vcn_v4_0_3_disable_clock_gating(adev, i);
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/* enable VCPU clock */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__CLK_EN_MASK,
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~UVD_VCPU_CNTL__CLK_EN_MASK);
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/* enable VCPU clock */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__CLK_EN_MASK,
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~UVD_VCPU_CNTL__CLK_EN_MASK);
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/* disable master interrupt */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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/* disable master interrupt */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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/* enable LMI MC and UMC channels */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* enable LMI MC and UMC channels */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
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tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
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tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
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WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
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tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
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tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
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WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
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/* setup regUVD_LMI_CTRL */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
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WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
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tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
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/* setup regUVD_LMI_CTRL */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
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WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
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tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
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/* setup regUVD_MPC_CNTL */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
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tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
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tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
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/* setup regUVD_MPC_CNTL */
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tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
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tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
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tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
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/* setup UVD_MPC_SET_MUXA0 */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
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((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
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/* setup UVD_MPC_SET_MUXA0 */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
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((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
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/* setup UVD_MPC_SET_MUXB0 */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
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((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
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/* setup UVD_MPC_SET_MUXB0 */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
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((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
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/* setup UVD_MPC_SET_MUX */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
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((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
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(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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/* setup UVD_MPC_SET_MUX */
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WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
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((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
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(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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vcn_v4_0_3_mc_resume(adev, i);
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vcn_v4_0_3_mc_resume(adev, i);
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/* VCN global tiling registers */
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WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* VCN global tiling registers */
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WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* unblock VCPU register access */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
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~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
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/* unblock VCPU register access */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
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~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
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/* release VCPU reset to boot */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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/* release VCPU reset to boot */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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for (j = 0; j < 10; ++j) {
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uint32_t status;
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for (j = 0; j < 10; ++j) {
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uint32_t status;
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for (k = 0; k < 100; ++k) {
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status = RREG32_SOC15(VCN, vcn_inst,
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regUVD_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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}
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r = 0;
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for (k = 0; k < 100; ++k) {
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status = RREG32_SOC15(VCN, vcn_inst,
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regUVD_STATUS);
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if (status & 2)
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break;
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DRM_DEV_ERROR(adev->dev,
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"VCN decode not responding, trying to reset the VCPU!!!\n");
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
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regUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__BLK_RST_MASK,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
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regUVD_VCPU_CNTL),
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0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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r = -1;
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}
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r = 0;
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if (status & 2)
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break;
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if (r) {
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DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
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return r;
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}
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/* enable master interrupt */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
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UVD_MASTINT_EN__VCPU_EN_MASK,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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/* clear the busy bit of VCN_STATUS */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
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ring = &adev->vcn.inst[i].ring_enc[0];
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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/* program the RB_BASE for ring buffer */
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
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ring->ring_size / sizeof(uint32_t));
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/* resetting ring, fw should not check RB ring */
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp |= VCN_RB_ENABLE__RB_EN_MASK;
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
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fw_shared->sq.queue_mode &=
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cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
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DRM_DEV_ERROR(adev->dev,
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"VCN decode not responding, trying to reset the VCPU!!!\n");
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
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regUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__BLK_RST_MASK,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
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regUVD_VCPU_CNTL),
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0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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r = -1;
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}
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if (r) {
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DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
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return r;
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}
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/* enable master interrupt */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
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UVD_MASTINT_EN__VCPU_EN_MASK,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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/* clear the busy bit of VCN_STATUS */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
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ring = &adev->vcn.inst[i].ring_enc[0];
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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/* program the RB_BASE for ring buffer */
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
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ring->ring_size / sizeof(uint32_t));
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/* resetting ring, fw should not check RB ring */
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp |= VCN_RB_ENABLE__RB_EN_MASK;
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
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fw_shared->sq.queue_mode &=
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cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
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return 0;
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}
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@ -1322,81 +1319,81 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
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* vcn_v4_0_3_stop - VCN stop
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*
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* @adev: amdgpu_device pointer
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* @i: instance to stop
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*
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* Stop VCN block
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*/
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static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
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static int vcn_v4_0_3_stop(struct amdgpu_device *adev, int i)
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{
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volatile struct amdgpu_vcn4_fw_shared *fw_shared;
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int i, r = 0, vcn_inst;
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int r = 0, vcn_inst;
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uint32_t tmp;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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vcn_inst = GET_INST(VCN, i);
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vcn_inst = GET_INST(VCN, i);
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
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vcn_v4_0_3_stop_dpg_mode(adev, i);
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continue;
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}
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/* wait for vcn idle */
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r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
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UVD_STATUS__IDLE, 0x7);
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if (r)
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goto Done;
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tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
|
||||
tmp);
|
||||
if (r)
|
||||
goto Done;
|
||||
|
||||
/* stall UMC channel */
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
|
||||
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
|
||||
tmp);
|
||||
if (r)
|
||||
goto Done;
|
||||
|
||||
/* Unblock VCPU Register access */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
|
||||
UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
|
||||
~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
|
||||
|
||||
/* release VCPU reset to boot */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
|
||||
UVD_VCPU_CNTL__BLK_RST_MASK,
|
||||
~UVD_VCPU_CNTL__BLK_RST_MASK);
|
||||
|
||||
/* disable VCPU clock */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
|
||||
~(UVD_VCPU_CNTL__CLK_EN_MASK));
|
||||
|
||||
/* reset LMI UMC/LMI/VCPU */
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
|
||||
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
|
||||
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
|
||||
|
||||
/* clear VCN status */
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
|
||||
|
||||
/* apply HW clock gating */
|
||||
vcn_v4_0_3_enable_clock_gating(adev, i);
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
|
||||
vcn_v4_0_3_stop_dpg_mode(adev, i);
|
||||
goto Done;
|
||||
}
|
||||
|
||||
/* wait for vcn idle */
|
||||
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
|
||||
UVD_STATUS__IDLE, 0x7);
|
||||
if (r)
|
||||
goto Done;
|
||||
|
||||
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
|
||||
tmp);
|
||||
if (r)
|
||||
goto Done;
|
||||
|
||||
/* stall UMC channel */
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
|
||||
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
|
||||
tmp);
|
||||
if (r)
|
||||
goto Done;
|
||||
|
||||
/* Unblock VCPU Register access */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
|
||||
UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
|
||||
~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
|
||||
|
||||
/* release VCPU reset to boot */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
|
||||
UVD_VCPU_CNTL__BLK_RST_MASK,
|
||||
~UVD_VCPU_CNTL__BLK_RST_MASK);
|
||||
|
||||
/* disable VCPU clock */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
|
||||
~(UVD_VCPU_CNTL__CLK_EN_MASK));
|
||||
|
||||
/* reset LMI UMC/LMI/VCPU */
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
|
||||
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
|
||||
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
|
||||
|
||||
/* clear VCN status */
|
||||
WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
|
||||
|
||||
/* apply HW clock gating */
|
||||
vcn_v4_0_3_enable_clock_gating(adev, i);
|
||||
|
||||
Done:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1653,7 +1650,7 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
|
|||
enum amd_powergating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int ret;
|
||||
int ret = 0, i;
|
||||
|
||||
/* for SRIOV, guest should not control VCN Power-gating
|
||||
* MMSCH FW should control Power-gating and clock-gating
|
||||
|
|
@ -1667,10 +1664,12 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
|
|||
if (state == adev->vcn.cur_state)
|
||||
return 0;
|
||||
|
||||
if (state == AMD_PG_STATE_GATE)
|
||||
ret = vcn_v4_0_3_stop(adev);
|
||||
else
|
||||
ret = vcn_v4_0_3_start(adev);
|
||||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
if (state == AMD_PG_STATE_GATE)
|
||||
ret |= vcn_v4_0_3_stop(adev, i);
|
||||
else
|
||||
ret |= vcn_v4_0_3_start(adev, i);
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
adev->vcn.cur_state = state;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user