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ARM: tegra: Device tree changes for v7.2-rc1
The bulk of this is various improvements for some of the older ASUS and
LG devices, but there's also support for interconnects on Tegra114 to
help improve memory frequency scaling.
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Merge tag 'tegra-for-7.2-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree changes for v7.2-rc1
The bulk of this is various improvements for some of the older ASUS and
LG devices, but there's also support for interconnects on Tegra114 to
help improve memory frequency scaling.
* tag 'tegra-for-7.2-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: tf600t: Invert accelerometer calibration matrix
ARM: tegra: tf600t: Drop backlight regulator
ARM: tegra: tf600t: Configure panel
ARM: tegra: transformers: Add connector node for common trees
ARM: tegra: transformer: Add support for front camera
ARM: tegra: grouper: Add support for front camera
ARM: tegra: p880: Lower CPU thermal limit
ARM: tegra: lg-x3: Set PMIC's RTC address
ARM: tegra: lg-x3: Complete video device graph
ARM: tegra: Configure Tegra114 power domains
ARM: tegra: Add DC interconnections for Tegra114
ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes
ARM: tegra: Add #{address,size}-cells to Chromium-based /firmware
dt-bindings: memory: Document Tegra114 External Memory Controller
dt-bindings: memory: Document Tegra114 Memory Controller
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
commit
57ffabf5a1
|
|
@ -16,7 +16,9 @@ description: |
|
|||
|
||||
properties:
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||||
compatible:
|
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const: nvidia,tegra124-emc
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enum:
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- nvidia,tegra114-emc
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||||
- nvidia,tegra124-emc
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -29,6 +31,9 @@ properties:
|
|||
items:
|
||||
- const: emc
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||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#interconnect-cells":
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const: 0
|
||||
|
||||
|
|
@ -164,153 +169,12 @@ patternProperties:
|
|||
nvidia,emc-configuration:
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description:
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EMC timing characterization data. These are the registers (see
|
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section "15.6.2 EMC Registers" in the TRM) whose values need to
|
||||
section "20.11.2 EMC Registers" in the Tegra114 TRM or section
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"15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
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be specified, according to the board documentation.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: EMC_RC
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- description: EMC_RFC
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- description: EMC_RFC_SLR
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- description: EMC_RAS
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- description: EMC_RP
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- description: EMC_R2W
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||||
- description: EMC_W2R
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- description: EMC_R2P
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||||
- description: EMC_W2P
|
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- description: EMC_RD_RCD
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- description: EMC_WR_RCD
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- description: EMC_RRD
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- description: EMC_REXT
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- description: EMC_WEXT
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- description: EMC_WDV
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- description: EMC_WDV_MASK
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- description: EMC_QUSE
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- description: EMC_QUSE_WIDTH
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- description: EMC_IBDLY
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- description: EMC_EINPUT
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- description: EMC_EINPUT_DURATION
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- description: EMC_PUTERM_EXTRA
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- description: EMC_PUTERM_WIDTH
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- description: EMC_PUTERM_ADJ
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- description: EMC_CDB_CNTL_1
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- description: EMC_CDB_CNTL_2
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- description: EMC_CDB_CNTL_3
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- description: EMC_QRST
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- description: EMC_QSAFE
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- description: EMC_RDV
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- description: EMC_RDV_MASK
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- description: EMC_REFRESH
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- description: EMC_BURST_REFRESH_NUM
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- description: EMC_PRE_REFRESH_REQ_CNT
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- description: EMC_PDEX2WR
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- description: EMC_PDEX2RD
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- description: EMC_PCHG2PDEN
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- description: EMC_ACT2PDEN
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- description: EMC_AR2PDEN
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- description: EMC_RW2PDEN
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- description: EMC_TXSR
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- description: EMC_TXSRDLL
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- description: EMC_TCKE
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- description: EMC_TCKESR
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- description: EMC_TPD
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- description: EMC_TFAW
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- description: EMC_TRPAB
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- description: EMC_TCLKSTABLE
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- description: EMC_TCLKSTOP
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- description: EMC_TREFBW
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- description: EMC_FBIO_CFG6
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- description: EMC_ODT_WRITE
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- description: EMC_ODT_READ
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- description: EMC_FBIO_CFG5
|
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- description: EMC_CFG_DIG_DLL
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- description: EMC_CFG_DIG_DLL_PERIOD
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- description: EMC_DLL_XFORM_DQS0
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- description: EMC_DLL_XFORM_DQS1
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- description: EMC_DLL_XFORM_DQS2
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- description: EMC_DLL_XFORM_DQS3
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- description: EMC_DLL_XFORM_DQS4
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- description: EMC_DLL_XFORM_DQS5
|
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- description: EMC_DLL_XFORM_DQS6
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- description: EMC_DLL_XFORM_DQS7
|
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- description: EMC_DLL_XFORM_DQS8
|
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- description: EMC_DLL_XFORM_DQS9
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- description: EMC_DLL_XFORM_DQS10
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- description: EMC_DLL_XFORM_DQS11
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- description: EMC_DLL_XFORM_DQS12
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- description: EMC_DLL_XFORM_DQS13
|
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- description: EMC_DLL_XFORM_DQS14
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- description: EMC_DLL_XFORM_DQS15
|
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- description: EMC_DLL_XFORM_QUSE0
|
||||
- description: EMC_DLL_XFORM_QUSE1
|
||||
- description: EMC_DLL_XFORM_QUSE2
|
||||
- description: EMC_DLL_XFORM_QUSE3
|
||||
- description: EMC_DLL_XFORM_QUSE4
|
||||
- description: EMC_DLL_XFORM_QUSE5
|
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- description: EMC_DLL_XFORM_QUSE6
|
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- description: EMC_DLL_XFORM_QUSE7
|
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- description: EMC_DLL_XFORM_ADDR0
|
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- description: EMC_DLL_XFORM_ADDR1
|
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- description: EMC_DLL_XFORM_ADDR2
|
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- description: EMC_DLL_XFORM_ADDR3
|
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- description: EMC_DLL_XFORM_ADDR4
|
||||
- description: EMC_DLL_XFORM_ADDR5
|
||||
- description: EMC_DLL_XFORM_QUSE8
|
||||
- description: EMC_DLL_XFORM_QUSE9
|
||||
- description: EMC_DLL_XFORM_QUSE10
|
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- description: EMC_DLL_XFORM_QUSE11
|
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- description: EMC_DLL_XFORM_QUSE12
|
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- description: EMC_DLL_XFORM_QUSE13
|
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- description: EMC_DLL_XFORM_QUSE14
|
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- description: EMC_DLL_XFORM_QUSE15
|
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- description: EMC_DLI_TRIM_TXDQS0
|
||||
- description: EMC_DLI_TRIM_TXDQS1
|
||||
- description: EMC_DLI_TRIM_TXDQS2
|
||||
- description: EMC_DLI_TRIM_TXDQS3
|
||||
- description: EMC_DLI_TRIM_TXDQS4
|
||||
- description: EMC_DLI_TRIM_TXDQS5
|
||||
- description: EMC_DLI_TRIM_TXDQS6
|
||||
- description: EMC_DLI_TRIM_TXDQS7
|
||||
- description: EMC_DLI_TRIM_TXDQS8
|
||||
- description: EMC_DLI_TRIM_TXDQS9
|
||||
- description: EMC_DLI_TRIM_TXDQS10
|
||||
- description: EMC_DLI_TRIM_TXDQS11
|
||||
- description: EMC_DLI_TRIM_TXDQS12
|
||||
- description: EMC_DLI_TRIM_TXDQS13
|
||||
- description: EMC_DLI_TRIM_TXDQS14
|
||||
- description: EMC_DLI_TRIM_TXDQS15
|
||||
- description: EMC_DLL_XFORM_DQ0
|
||||
- description: EMC_DLL_XFORM_DQ1
|
||||
- description: EMC_DLL_XFORM_DQ2
|
||||
- description: EMC_DLL_XFORM_DQ3
|
||||
- description: EMC_DLL_XFORM_DQ4
|
||||
- description: EMC_DLL_XFORM_DQ5
|
||||
- description: EMC_DLL_XFORM_DQ6
|
||||
- description: EMC_DLL_XFORM_DQ7
|
||||
- description: EMC_XM2CMDPADCTRL
|
||||
- description: EMC_XM2CMDPADCTRL4
|
||||
- description: EMC_XM2CMDPADCTRL5
|
||||
- description: EMC_XM2DQPADCTRL2
|
||||
- description: EMC_XM2DQPADCTRL3
|
||||
- description: EMC_XM2CLKPADCTRL
|
||||
- description: EMC_XM2CLKPADCTRL2
|
||||
- description: EMC_XM2COMPPADCTRL
|
||||
- description: EMC_XM2VTTGENPADCTRL
|
||||
- description: EMC_XM2VTTGENPADCTRL2
|
||||
- description: EMC_XM2VTTGENPADCTRL3
|
||||
- description: EMC_XM2DQSPADCTRL3
|
||||
- description: EMC_XM2DQSPADCTRL4
|
||||
- description: EMC_XM2DQSPADCTRL5
|
||||
- description: EMC_XM2DQSPADCTRL6
|
||||
- description: EMC_DSR_VTTGEN_DRV
|
||||
- description: EMC_TXDSRVTTGEN
|
||||
- description: EMC_FBIO_SPARE
|
||||
- description: EMC_ZCAL_WAIT_CNT
|
||||
- description: EMC_MRS_WAIT_CNT2
|
||||
- description: EMC_CTT
|
||||
- description: EMC_CTT_DURATION
|
||||
- description: EMC_CFG_PIPE
|
||||
- description: EMC_DYN_SELF_REF_CONTROL
|
||||
- description: EMC_QPOP
|
||||
minItems: 97
|
||||
maxItems: 143
|
||||
|
||||
required:
|
||||
- clock-frequency
|
||||
|
|
@ -318,9 +182,7 @@ patternProperties:
|
|||
- nvidia,emc-auto-cal-config2
|
||||
- nvidia,emc-auto-cal-config3
|
||||
- nvidia,emc-auto-cal-interval
|
||||
- nvidia,emc-bgbias-ctl0
|
||||
- nvidia,emc-cfg
|
||||
- nvidia,emc-cfg-2
|
||||
- nvidia,emc-ctt-term-ctrl
|
||||
- nvidia,emc-mode-1
|
||||
- nvidia,emc-mode-2
|
||||
|
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@ -344,6 +206,22 @@ required:
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- "#interconnect-cells"
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- operating-points-v2
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allOf:
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- if:
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properties:
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compatible:
|
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contains:
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enum:
|
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- nvidia,tegra124-emc
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then:
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patternProperties:
|
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"^emc-timings-[0-9]+$":
|
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patternProperties:
|
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"^timing-[0-9]+$":
|
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required:
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- nvidia,emc-bgbias-ctl0
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- nvidia,emc-cfg-2
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additionalProperties: false
|
||||
|
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examples:
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ description: |
|
|||
|
||||
properties:
|
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compatible:
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const: nvidia,tegra124-mc
|
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enum:
|
||||
- nvidia,tegra114-mc
|
||||
- nvidia,tegra124-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -64,29 +66,12 @@ patternProperties:
|
|||
|
||||
nvidia,emem-configuration:
|
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$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
description:
|
||||
Values to be written to the EMEM register block. See section
|
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"15.6.1 MC Registers" in the TRM.
|
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items:
|
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- description: MC_EMEM_ARB_CFG
|
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- description: MC_EMEM_ARB_OUTSTANDING_REQ
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- description: MC_EMEM_ARB_TIMING_RCD
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- description: MC_EMEM_ARB_TIMING_RP
|
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- description: MC_EMEM_ARB_TIMING_RC
|
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- description: MC_EMEM_ARB_TIMING_RAS
|
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- description: MC_EMEM_ARB_TIMING_FAW
|
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- description: MC_EMEM_ARB_TIMING_RRD
|
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- description: MC_EMEM_ARB_TIMING_RAP2PRE
|
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- description: MC_EMEM_ARB_TIMING_WAP2PRE
|
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- description: MC_EMEM_ARB_TIMING_R2R
|
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- description: MC_EMEM_ARB_TIMING_W2W
|
||||
- description: MC_EMEM_ARB_TIMING_R2W
|
||||
- description: MC_EMEM_ARB_TIMING_W2R
|
||||
- description: MC_EMEM_ARB_DA_TURNS
|
||||
- description: MC_EMEM_ARB_DA_COVERS
|
||||
- description: MC_EMEM_ARB_MISC0
|
||||
- description: MC_EMEM_ARB_MISC1
|
||||
- description: MC_EMEM_ARB_RING1_THROTTLE
|
||||
"20.11.1 MC Registers" in the Tegea114 TRM or
|
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"15.6.1 MC Registers" in the Tegra124 TRM.
|
||||
minItems: 18
|
||||
maxItems: 19
|
||||
|
||||
required:
|
||||
- clock-frequency
|
||||
|
|
|
|||
1439
arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
Normal file
1439
arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -8,6 +8,8 @@
|
|||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
#include <dt-bindings/thermal/tegra114-soctherm.h>
|
||||
|
||||
#include "tegra114-peripherals-opp.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,tegra114";
|
||||
interrupt-parent = <&lic>;
|
||||
|
|
@ -56,6 +58,8 @@ vi@54080000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_VI>;
|
||||
resets = <&tegra_car 20>;
|
||||
reset-names = "vi";
|
||||
power-domains = <&pd_venc>;
|
||||
operating-points-v2 = <&vi_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_VI>;
|
||||
|
||||
|
|
@ -69,6 +73,8 @@ epp@540c0000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_EPP>;
|
||||
resets = <&tegra_car TEGRA114_CLK_EPP>;
|
||||
reset-names = "epp";
|
||||
power-domains = <&pd_heg>;
|
||||
operating-points-v2 = <&epp_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_EPP>;
|
||||
|
||||
|
|
@ -82,6 +88,7 @@ isp@54100000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_ISP>;
|
||||
resets = <&tegra_car TEGRA114_CLK_ISP>;
|
||||
reset-names = "isp";
|
||||
power-domains = <&pd_venc>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_ISP>;
|
||||
|
||||
|
|
@ -95,6 +102,8 @@ gr2d@54140000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_GR2D>;
|
||||
resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
|
||||
reset-names = "2d", "mc";
|
||||
power-domains = <&pd_heg>;
|
||||
operating-points-v2 = <&gr2d_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_G2>;
|
||||
};
|
||||
|
|
@ -105,6 +114,8 @@ gr3d@54180000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
|
||||
reset-names = "3d", "mc";
|
||||
power-domains = <&pd_3d>;
|
||||
operating-points-v2 = <&gr3d_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_NV>;
|
||||
};
|
||||
|
|
@ -118,11 +129,24 @@ dc@54200000 {
|
|||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&disp1_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_DC>;
|
||||
|
||||
nvidia,head = <0>;
|
||||
|
||||
interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY0B &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY1B &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY0C &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAYHC &emc>;
|
||||
interconnect-names = "wina",
|
||||
"winb",
|
||||
"winb-vfilter",
|
||||
"winc",
|
||||
"cursor";
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -137,11 +161,24 @@ dc@54240000 {
|
|||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&disp2_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_DCB>;
|
||||
|
||||
nvidia,head = <1>;
|
||||
|
||||
interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY0BB &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY1BB &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAY0CB &emc>,
|
||||
<&mc TEGRA114_MC_DISPLAYHCB &emc>;
|
||||
interconnect-names = "wina",
|
||||
"winb",
|
||||
"winb-vfilter",
|
||||
"winc",
|
||||
"cursor";
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -156,6 +193,8 @@ hdmi@54280000 {
|
|||
clock-names = "hdmi", "parent";
|
||||
resets = <&tegra_car 51>;
|
||||
reset-names = "hdmi";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&hdmi_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -169,6 +208,7 @@ dsia: dsi@54300000 {
|
|||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -185,6 +225,7 @@ dsib: dsi@54400000 {
|
|||
resets = <&tegra_car 82>;
|
||||
reset-names = "dsi";
|
||||
nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -198,6 +239,8 @@ msenc@544c0000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_MSENC>;
|
||||
resets = <&tegra_car TEGRA114_CLK_MSENC>;
|
||||
reset-names = "mpe";
|
||||
power-domains = <&pd_mpe>;
|
||||
operating-points-v2 = <&msenc_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_MSENC>;
|
||||
|
||||
|
|
@ -210,6 +253,8 @@ tsec@54500000 {
|
|||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
|
||||
resets = <&tegra_car TEGRA114_CLK_TSEC>;
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&tsec_dvfs_opp_table>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_TSEC>;
|
||||
|
||||
|
|
@ -323,6 +368,9 @@ actmon: actmon@6000c800 {
|
|||
clock-names = "actmon", "emc";
|
||||
resets = <&tegra_car TEGRA114_CLK_ACTMON>;
|
||||
reset-names = "actmon";
|
||||
operating-points-v2 = <&emc_bw_dfs_opp_table>;
|
||||
interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
|
||||
interconnect-names = "cpu-read";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
|
|
@ -366,6 +414,8 @@ vde@6001a000 {
|
|||
reset-names = "vde", "mc";
|
||||
resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
|
||||
iommus = <&mc TEGRA_SWGROUP_VDE>;
|
||||
power-domains = <&pd_vde>;
|
||||
operating-points-v2 = <&vde_dvfs_opp_table>;
|
||||
};
|
||||
|
||||
apbmisc@70000800 {
|
||||
|
|
@ -443,6 +493,7 @@ pwm: pwm@7000a000 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_PWM>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -533,6 +584,8 @@ spi@7000d400 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 15>, <&apbdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc1_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -548,6 +601,8 @@ spi@7000d600 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc2_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -563,6 +618,8 @@ spi@7000d800 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 17>, <&apbdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc3_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -578,6 +635,8 @@ spi@7000da00 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 18>, <&apbdma 18>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc4_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -593,6 +652,8 @@ spi@7000dc00 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 27>, <&apbdma 27>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc5_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -608,6 +669,8 @@ spi@7000de00 {
|
|||
reset-names = "spi";
|
||||
dmas = <&apbdma 28>, <&apbdma 28>;
|
||||
dma-names = "rx", "tx";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sbc6_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -634,6 +697,86 @@ tegra_pmc: pmc@7000e400 {
|
|||
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
pd_core: core-domain {
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&core_opp_table>;
|
||||
};
|
||||
|
||||
powergates {
|
||||
/*
|
||||
* TODO: Add DIS and DISB domains once DC is able
|
||||
* to handle them properly. VENC and DISB should
|
||||
* set DIS as their source power domain due to
|
||||
* internal dependency.
|
||||
*/
|
||||
|
||||
pd_heg: heg {
|
||||
clocks = <&tegra_car TEGRA114_CLK_GR2D>,
|
||||
<&tegra_car TEGRA114_CLK_EPP>;
|
||||
resets = <&mc TEGRA114_MC_RESET_2D>,
|
||||
<&mc TEGRA114_MC_RESET_EPP>,
|
||||
<&tegra_car TEGRA114_CLK_GR2D>,
|
||||
<&tegra_car TEGRA114_CLK_EPP>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_mpe: mpe {
|
||||
clocks = <&tegra_car TEGRA114_CLK_MSENC>;
|
||||
resets = <&mc TEGRA114_MC_RESET_MPE>,
|
||||
<&tegra_car TEGRA114_CLK_MSENC>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_3d: td {
|
||||
clocks = <&tegra_car TEGRA114_CLK_GR3D>;
|
||||
resets = <&mc TEGRA114_MC_RESET_3D>,
|
||||
<&tegra_car TEGRA114_CLK_GR3D>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_vde: vdec {
|
||||
clocks = <&tegra_car TEGRA114_CLK_VDE>;
|
||||
resets = <&mc TEGRA114_MC_RESET_VDE>,
|
||||
<&tegra_car TEGRA114_CLK_VDE>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_venc: venc {
|
||||
clocks = <&tegra_car TEGRA114_CLK_ISP>,
|
||||
<&tegra_car TEGRA114_CLK_VI>,
|
||||
<&tegra_car TEGRA114_CLK_CSI>;
|
||||
resets = <&mc TEGRA114_MC_RESET_ISP>,
|
||||
<&mc TEGRA114_MC_RESET_VI>,
|
||||
<&tegra_car TEGRA114_CLK_ISP>,
|
||||
<&tegra_car 20 /* VI */>,
|
||||
<&tegra_car TEGRA114_CLK_CSI>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA114_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA114_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbdev: xusbb {
|
||||
clocks = <&tegra_car TEGRA114_CLK_XUSB_DEV>;
|
||||
resets = <&tegra_car 95>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbhost: xusbc {
|
||||
clocks = <&tegra_car TEGRA114_CLK_XUSB_HOST>;
|
||||
resets = <&tegra_car TEGRA114_CLK_XUSB_HOST>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fuse@7000f800 {
|
||||
|
|
@ -643,6 +786,7 @@ fuse@7000f800 {
|
|||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
power-domains = <&pd_core>;
|
||||
};
|
||||
|
||||
mc: memory-controller@70019000 {
|
||||
|
|
@ -655,6 +799,7 @@ mc: memory-controller@70019000 {
|
|||
|
||||
#reset-cells = <1>;
|
||||
#iommu-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
emc: external-memory-controller@7001b000 {
|
||||
|
|
@ -663,8 +808,12 @@ emc: external-memory-controller@7001b000 {
|
|||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
power-domains = <&pd_core>;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
};
|
||||
|
||||
hda@70030000 {
|
||||
|
|
@ -854,6 +1003,8 @@ mmc@78000000 {
|
|||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -876,6 +1027,8 @@ mmc@78000400 {
|
|||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -887,6 +1040,8 @@ mmc@78000600 {
|
|||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
power-domains = <&pd_core>;
|
||||
operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -899,6 +1054,7 @@ usb@7d000000 {
|
|||
resets = <&tegra_car 22>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy1>;
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -939,6 +1095,7 @@ usb@7d008000 {
|
|||
resets = <&tegra_car 59>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy3>;
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,11 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
firmware {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Note that recent version of the device tree compiler (starting with
|
||||
* version 1.4.2) warn about this node containing a reg property, but
|
||||
|
|
|
|||
|
|
@ -18,6 +18,11 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
firmware {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,9 +79,11 @@ hdmi@54280000 {
|
|||
pll-supply = <&hdmi_pll_reg>;
|
||||
hdmi-supply = <&vdd_hdmi_en>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1017,6 +1019,20 @@ key-volume-up {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "d";
|
||||
|
||||
hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
|
||||
ddc-i2c-bus = <&hdmi_ddc>;
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2cmux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/media/video-interfaces.h>
|
||||
#include <dt-bindings/power/summit,smb347-charger.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
|
|
@ -84,6 +85,93 @@ init-mode-hog {
|
|||
};
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
vi@54080000 {
|
||||
status = "okay";
|
||||
|
||||
csi@800 {
|
||||
status = "okay";
|
||||
|
||||
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
|
||||
|
||||
/* CSI-A */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csia_input: endpoint {
|
||||
data-lanes = <1 2>;
|
||||
/* No rear camera */
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csia_output: endpoint {
|
||||
remote-endpoint = <&vi_ppa_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CSI-B */
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csib_input: endpoint {
|
||||
data-lanes = <3>;
|
||||
remote-endpoint = <&front_camera_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csib_output: endpoint {
|
||||
remote-endpoint = <&vi_ppb_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
vi_ppa_input: endpoint {
|
||||
remote-endpoint = <&csia_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
vi_ppb_input: endpoint {
|
||||
remote-endpoint = <&csib_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
|
@ -890,6 +978,36 @@ light-sensor@1c {
|
|||
vdd-supply = <&vdd_3v3_sys>;
|
||||
};
|
||||
|
||||
/* Aptina 1/6" HD SOC (MI1040) */
|
||||
front-camera@48 {
|
||||
compatible = "aptina,mi1040";
|
||||
reg = <0x48>;
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_CSUS>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA_GPIO(O, 0) GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddio-supply = <&avdd_cam1>;
|
||||
vdd-supply = <&vddio_cam>;
|
||||
vaa-supply = <&avdd_cam1>;
|
||||
|
||||
orientation = <0>; /* Front camera */
|
||||
|
||||
assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,
|
||||
<&tegra_car TEGRA30_CLK_CSUS>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
|
||||
<&tegra_car TEGRA30_CLK_VI_SENSOR>;
|
||||
|
||||
port {
|
||||
front_camera_output: endpoint {
|
||||
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
|
||||
link-frequencies = /bits/ 64 <384000000>;
|
||||
remote-endpoint = <&csib_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
accelerometer@68 {
|
||||
compatible = "invensense,mpu6050";
|
||||
reg = <0x68>;
|
||||
|
|
@ -1203,6 +1321,16 @@ vcc_3v3_ts: regulator-ts {
|
|||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
avdd_cam1: regulator-vcam1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "avdd_cam1";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-rt5640-grouper",
|
||||
"nvidia,tegra-audio-rt5640";
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ ldo4 {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo5 {
|
||||
vddio_cam: ldo5 {
|
||||
regulator-name = "vdd_camera";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
|
@ -149,7 +149,7 @@ ldo6 {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo7 {
|
||||
avdd_dsi_csi: ldo7 {
|
||||
regulator-name = "avdd_dsi_csi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
|
|
|||
|
|
@ -92,13 +92,13 @@ ldo4 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5 {
|
||||
vddio_cam: ldo5 {
|
||||
regulator-name = "vddio_sdmmc,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo6 {
|
||||
avdd_dsi_csi: ldo6 {
|
||||
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ aliases {
|
|||
rtc0 = &pmic;
|
||||
rtc1 = "/rtc@7000e000";
|
||||
|
||||
display0 = &lcd;
|
||||
display1 = &hdmi;
|
||||
|
||||
serial1 = &uartc; /* Bluetooth */
|
||||
|
|
@ -55,6 +56,37 @@ linux,cma@80000000 {
|
|||
};
|
||||
|
||||
host1x@50000000 {
|
||||
vi@54080000 {
|
||||
status = "okay";
|
||||
|
||||
csi@800 {
|
||||
status = "okay";
|
||||
|
||||
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
vi_ppa_input: endpoint {
|
||||
/* Link to the rear camera */
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
vi_ppb_input: endpoint {
|
||||
/* Link to the front camera */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -68,6 +100,22 @@ hdmi_out: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcd: dsi@54300000 {
|
||||
status = "okay";
|
||||
|
||||
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "hydis,hv101hd1";
|
||||
reg = <0>;
|
||||
|
||||
vdd-supply = <&vdd_panel>;
|
||||
vio-supply = <&vio_panel>;
|
||||
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vde@6001a000 {
|
||||
|
|
@ -1043,9 +1091,9 @@ imu@69 {
|
|||
vdd-supply = <&vdd_3v3_sys>;
|
||||
vddio-supply = <&vdd_1v8_vio>;
|
||||
|
||||
mount-matrix = "0", "-1", "0",
|
||||
"-1", "0", "0",
|
||||
"0", "0", "-1";
|
||||
mount-matrix = "0", "1", "0",
|
||||
"1", "0", "0",
|
||||
"0", "0", "1";
|
||||
|
||||
/* External I2C interface */
|
||||
i2c-gate {
|
||||
|
|
@ -1123,11 +1171,10 @@ pmic-sleep-hog {
|
|||
};
|
||||
|
||||
regulators {
|
||||
vdd_lcd: vdd1 {
|
||||
vio_panel: vdd1 {
|
||||
regulator-name = "vddio_ddr_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
ti,regulator-ext-sleep-control = <8>;
|
||||
};
|
||||
|
|
@ -2145,7 +2192,7 @@ backlight: backlight {
|
|||
compatible = "pwm-backlight";
|
||||
|
||||
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vdd_5v0_bl>;
|
||||
power-supply = <&vdd_5v0_sys>;
|
||||
pwms = <&pwm 0 71428>;
|
||||
|
||||
brightness-levels = <1 255>;
|
||||
|
|
@ -2375,15 +2422,15 @@ vdd_3v3_als: regulator-als {
|
|||
vin-supply = <&vdd_3v3_sys>;
|
||||
};
|
||||
|
||||
vdd_5v0_bl: regulator-bl {
|
||||
vdd_panel: regulator-panel {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v0_bl";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vdd_panel";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
|
||||
gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd_5v0_bat>;
|
||||
vin-supply = <&vdd_3v3_sys>;
|
||||
};
|
||||
|
||||
hdmi_5v0_sys: regulator-hdmi {
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/media/video-interfaces.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
#include "tegra30.dtsi"
|
||||
|
|
@ -73,6 +74,91 @@ trustzone@bfe00000 {
|
|||
};
|
||||
|
||||
host1x@50000000 {
|
||||
vi@54080000 {
|
||||
status = "okay";
|
||||
|
||||
csi@800 {
|
||||
status = "okay";
|
||||
|
||||
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
|
||||
|
||||
/* CSI-A */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csia_input: endpoint {
|
||||
data-lanes = <1 2>;
|
||||
/* Add rear camera */
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csia_output: endpoint {
|
||||
remote-endpoint = <&vi_ppa_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CSI-B */
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csib_input: endpoint {
|
||||
data-lanes = <3>;
|
||||
remote-endpoint = <&front_camera_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csib_output: endpoint {
|
||||
remote-endpoint = <&vi_ppb_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
vi_ppa_input: endpoint {
|
||||
remote-endpoint = <&csia_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
vi_ppb_input: endpoint {
|
||||
remote-endpoint = <&csib_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -80,8 +166,11 @@ hdmi: hdmi@54280000 {
|
|||
pll-supply = <&vdd_1v8_vio>;
|
||||
vdd-supply = <&vdd_3v3_sys>;
|
||||
|
||||
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1160,6 +1249,36 @@ light-sensor@1c {
|
|||
vdd-supply = <&vdd_3v3_sys>;
|
||||
};
|
||||
|
||||
/* Aptina 1/6" HD SOC (MI1040) */
|
||||
front-camera@48 {
|
||||
compatible = "aptina,mi1040";
|
||||
reg = <0x48>;
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_CSUS>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA_GPIO(O, 0) GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddio-supply = <&vdd_1v8_cam>;
|
||||
vdd-supply = <&vdd_1v8_cam>;
|
||||
vaa-supply = <&avdd_2v85_fcam>;
|
||||
|
||||
orientation = <0>; /* Front camera */
|
||||
|
||||
assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,
|
||||
<&tegra_car TEGRA30_CLK_CSUS>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
|
||||
<&tegra_car TEGRA30_CLK_VI_SENSOR>;
|
||||
|
||||
port {
|
||||
front_camera_output: endpoint {
|
||||
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
|
||||
link-frequencies = /bits/ 64 <384000000>;
|
||||
remote-endpoint = <&csib_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gyroscope@68 {
|
||||
compatible = "invensense,mpu3050";
|
||||
reg = <0x68>;
|
||||
|
|
@ -1297,7 +1416,7 @@ ldo4 {
|
|||
|
||||
/* LDO5 is not used by Transformers */
|
||||
|
||||
ldo6 {
|
||||
avdd_dsi_csi: ldo6 {
|
||||
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
|
@ -1572,6 +1691,20 @@ key-volume-up {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "d";
|
||||
|
||||
hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
|
||||
ddc-i2c-bus = <&hdmi_ddc>;
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v0_bat: regulator-bat {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_ac_bat";
|
||||
|
|
@ -1672,6 +1805,26 @@ hdmi_5v0_sys: regulator-hdmi {
|
|||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
vdd_1v8_cam: regulator-viocam {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_1v8_cam";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd_1v8_vio>;
|
||||
};
|
||||
|
||||
avdd_2v85_fcam: regulator-avcam-front {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_2v85_fcam";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd_3v3_sys>;
|
||||
};
|
||||
|
||||
sound {
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,18 @@ aliases {
|
|||
mmc2 = &sdmmc1; /* WiFi */
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
vi@54080000 {
|
||||
csi@800 {
|
||||
/delete-node/ channel@1;
|
||||
};
|
||||
|
||||
ports {
|
||||
/delete-node/ port@1;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
|
@ -116,6 +128,22 @@ rmi4-f11@11 {
|
|||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
camera-pmic@7d {
|
||||
vt_1v2_front: ldo1 {
|
||||
regulator-name = "vt_1v2_dig";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vt_2v7_front: ldo2 {
|
||||
regulator-name = "vt_2v7_vana";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000dc00 {
|
||||
dsi@2 {
|
||||
/*
|
||||
|
|
@ -509,4 +537,17 @@ sound {
|
|||
|
||||
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
trips {
|
||||
cpu-alert {
|
||||
/* throttle at 60C until temperature drops to 59.8C */
|
||||
temperature = <60000>;
|
||||
hysteresis = <200>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -118,6 +118,52 @@ rmi4-f1a@1a {
|
|||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
/* Aptina 1/6" HD SOC (MT9M114) */
|
||||
front-camera@48 {
|
||||
compatible = "onnn,mt9m114";
|
||||
reg = <0x48>;
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_CSUS>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddio-supply = <&vio_1v8_front>;
|
||||
vdd-supply = <&vt_1v8_front>;
|
||||
vaa-supply = <&vt_2v8_front>;
|
||||
|
||||
orientation = <0>; /* Front camera */
|
||||
|
||||
assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,
|
||||
<&tegra_car TEGRA30_CLK_CSUS>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
|
||||
<&tegra_car TEGRA30_CLK_VI_SENSOR>;
|
||||
|
||||
port {
|
||||
front_camera_output: endpoint {
|
||||
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
|
||||
link-frequencies = /bits/ 64 <384000000>;
|
||||
remote-endpoint = <&csib_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camera-pmic@7d {
|
||||
vt_1v8_front: ldo1 {
|
||||
regulator-name = "vt_1v8_dig";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vt_2v8_front: ldo2 {
|
||||
regulator-name = "vt_2v8_vana";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000dc00 {
|
||||
dsi@2 {
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/media/video-interfaces.h>
|
||||
#include <dt-bindings/mfd/max77620.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
|
|
@ -74,6 +75,91 @@ trustzone@bfe00000 {
|
|||
};
|
||||
|
||||
host1x@50000000 {
|
||||
vi@54080000 {
|
||||
status = "okay";
|
||||
|
||||
csi@800 {
|
||||
status = "okay";
|
||||
|
||||
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
|
||||
|
||||
/* CSI-A */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csia_input: endpoint {
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&rear_camera_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csia_output: endpoint {
|
||||
remote-endpoint = <&vi_ppa_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CSI-B */
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
|
||||
nvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csib_input: endpoint {
|
||||
data-lanes = <3>;
|
||||
remote-endpoint = <&front_camera_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csib_output: endpoint {
|
||||
remote-endpoint = <&vi_ppb_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
vi_ppa_input: endpoint {
|
||||
remote-endpoint = <&csia_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
vi_ppb_input: endpoint {
|
||||
remote-endpoint = <&csib_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcd: dc@54200000 {
|
||||
rgb {
|
||||
status = "okay";
|
||||
|
|
@ -1112,29 +1198,68 @@ dw9714: coil@c {
|
|||
compatible = "dongwoon,dw9714";
|
||||
reg = <0x0c>;
|
||||
|
||||
enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>;
|
||||
powerdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vcc_focuser>;
|
||||
};
|
||||
|
||||
/* SONY IMX111 1/4" BSI */
|
||||
rear-camera@10 {
|
||||
compatible = "sony,imx111";
|
||||
reg = <0x10>;
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_CSUS>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>;
|
||||
|
||||
iovdd-supply = <&vio_1v8_rear>;
|
||||
dvdd-supply = <&vdd_1v2_rear>;
|
||||
avdd-supply = <&vdd_2v7_rear>;
|
||||
|
||||
orientation = <1>; /* Rear camera */
|
||||
rotation = <90>;
|
||||
|
||||
nvmem = <&m24c08>;
|
||||
lens-focus = <&dw9714>;
|
||||
|
||||
assigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,
|
||||
<&tegra_car TEGRA30_CLK_CSUS>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
|
||||
<&tegra_car TEGRA30_CLK_VI_SENSOR>;
|
||||
|
||||
port {
|
||||
rear_camera_output: endpoint {
|
||||
data-lanes = <1 2>;
|
||||
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
|
||||
link-frequencies = /bits/ 64 <542400000>;
|
||||
remote-endpoint = <&csia_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* rear camera sensor eeprom m24c08 from ST */
|
||||
m24c08: eeprom@50 {
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x50>;
|
||||
|
||||
/* if high then WP is on, if low then off */
|
||||
wp-gpios = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* it is not OTP but writing is unwanted */
|
||||
read-only;
|
||||
pagesize = <16>;
|
||||
num-addresses = <1>;
|
||||
|
||||
vcc-supply = <&vio_1v8_rear>;
|
||||
};
|
||||
|
||||
camera-pmic@7d {
|
||||
compatible = "ti,lp8720";
|
||||
reg = <0x7d>;
|
||||
|
||||
enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vt_1v2_front: ldo1 {
|
||||
regulator-name = "vt_1v2_dig";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vt_2v7_front: ldo2 {
|
||||
regulator-name = "vt_2v7_vana";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
vdd_2v7_rear: ldo3 {
|
||||
regulator-name = "8m_2v7_vana";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
|
|
@ -1172,7 +1297,8 @@ pwr_i2c: i2c@7000d000 {
|
|||
|
||||
pmic: max77663@1c {
|
||||
compatible = "maxim,max77663";
|
||||
reg = <0x1c>;
|
||||
reg = <0x1c>, <0x48>;
|
||||
reg-names = "pmic", "rtc";
|
||||
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -1348,10 +1474,11 @@ vdd_1v2_mhl: ldo7 {
|
|||
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
||||
};
|
||||
|
||||
ldo8 {
|
||||
avdd_dsi_csi: ldo8 {
|
||||
regulator-name = "avdd_dsi_csi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-boot-on;
|
||||
|
||||
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,4 +40,71 @@
|
|||
#define TEGRA114_MC_RESET_VDE 14
|
||||
#define TEGRA114_MC_RESET_VI 15
|
||||
|
||||
#define TEGRA114_MC_PTCR 0
|
||||
#define TEGRA114_MC_DISPLAY0A 1
|
||||
#define TEGRA114_MC_DISPLAY0AB 2
|
||||
#define TEGRA114_MC_DISPLAY0B 3
|
||||
#define TEGRA114_MC_DISPLAY0BB 4
|
||||
#define TEGRA114_MC_DISPLAY0C 5
|
||||
#define TEGRA114_MC_DISPLAY0CB 6
|
||||
#define TEGRA114_MC_DISPLAY1B 7
|
||||
#define TEGRA114_MC_DISPLAY1BB 8
|
||||
#define TEGRA114_MC_EPPUP 9
|
||||
#define TEGRA114_MC_G2PR 10
|
||||
#define TEGRA114_MC_G2SR 11
|
||||
#define TEGRA114_MC_MPEUNIFBR 12
|
||||
#define TEGRA114_MC_VIRUV 13
|
||||
#define TEGRA114_MC_AFIR 14
|
||||
#define TEGRA114_MC_AVPCARM7R 15
|
||||
#define TEGRA114_MC_DISPLAYHC 16
|
||||
#define TEGRA114_MC_DISPLAYHCB 17
|
||||
#define TEGRA114_MC_FDCDRD 18
|
||||
#define TEGRA114_MC_FDCDRD2 19
|
||||
#define TEGRA114_MC_G2DR 20
|
||||
#define TEGRA114_MC_HDAR 21
|
||||
#define TEGRA114_MC_HOST1XDMAR 22
|
||||
#define TEGRA114_MC_HOST1XR 23
|
||||
#define TEGRA114_MC_IDXSRD 24
|
||||
#define TEGRA114_MC_IDXSRD2 25
|
||||
#define TEGRA114_MC_MPE_IPRED 26
|
||||
#define TEGRA114_MC_MPEAMEMRD 27
|
||||
#define TEGRA114_MC_MPECSRD 28
|
||||
#define TEGRA114_MC_PPCSAHBDMAR 29
|
||||
#define TEGRA114_MC_PPCSAHBSLVR 30
|
||||
#define TEGRA114_MC_SATAR 31
|
||||
#define TEGRA114_MC_TEXSRD 32
|
||||
#define TEGRA114_MC_TEXSRD2 33
|
||||
#define TEGRA114_MC_VDEBSEVR 34
|
||||
#define TEGRA114_MC_VDEMBER 35
|
||||
#define TEGRA114_MC_VDEMCER 36
|
||||
#define TEGRA114_MC_VDETPER 37
|
||||
#define TEGRA114_MC_MPCORELPR 38
|
||||
#define TEGRA114_MC_MPCORER 39
|
||||
#define TEGRA114_MC_EPPU 40
|
||||
#define TEGRA114_MC_EPPV 41
|
||||
#define TEGRA114_MC_EPPY 42
|
||||
#define TEGRA114_MC_MPEUNIFBW 43
|
||||
#define TEGRA114_MC_VIWSB 44
|
||||
#define TEGRA114_MC_VIWU 45
|
||||
#define TEGRA114_MC_VIWV 46
|
||||
#define TEGRA114_MC_VIWY 47
|
||||
#define TEGRA114_MC_G2DW 48
|
||||
#define TEGRA114_MC_AFIW 49
|
||||
#define TEGRA114_MC_AVPCARM7W 50
|
||||
#define TEGRA114_MC_FDCDWR 51
|
||||
#define TEGRA114_MC_FDCDWR2 52
|
||||
#define TEGRA114_MC_HDAW 53
|
||||
#define TEGRA114_MC_HOST1XW 54
|
||||
#define TEGRA114_MC_ISPW 55
|
||||
#define TEGRA114_MC_MPCORELPW 56
|
||||
#define TEGRA114_MC_MPCOREW 57
|
||||
#define TEGRA114_MC_MPECSWR 58
|
||||
#define TEGRA114_MC_PPCSAHBDMAW 59
|
||||
#define TEGRA114_MC_PPCSAHBSLVW 60
|
||||
#define TEGRA114_MC_SATAW 61
|
||||
#define TEGRA114_MC_VDEBSEVW 62
|
||||
#define TEGRA114_MC_VDEDBGW 63
|
||||
#define TEGRA114_MC_VDEMBEW 64
|
||||
#define TEGRA114_MC_VDETPMW 65
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user