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wifi: iwlwifi: pcie: move pm_support to the specific transport
Currently it is under iwl_trans, which is the bus agnostic part of the transport. But really it is relevant for pcie only, so move it to the iwl_trans_pcie and export it via an API to the opmode. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.997193cabd04.Ic6648f040430c94150d0fa11601f50a6a630b862@changeid
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@ -368,7 +368,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
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/* initialize to default */
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void iwl_power_initialize(struct iwl_priv *priv)
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{
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priv->power_data.bus_pm = priv->trans->pm_support;
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priv->power_data.bus_pm = iwl_trans_is_pm_supported(priv->trans);
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priv->power_data.debug_sleep_level_override = -1;
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@ -807,3 +807,12 @@ void iwl_trans_set_reduce_power(struct iwl_trans *trans,
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{
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iwl_trans_pcie_ctx_info_v2_set_reduce_power(trans, capa);
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}
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bool iwl_trans_is_pm_supported(struct iwl_trans *trans)
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{
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if (WARN_ON(trans->mac_cfg->gen2))
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return false;
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return iwl_pcie_gen1_is_pm_supported(trans);
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}
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IWL_EXPORT_SYMBOL(iwl_trans_is_pm_supported);
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@ -844,7 +844,6 @@ struct iwl_trans_info {
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* @dev: pointer to struct device * that represents the device
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* @info: device information for use by other layers
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* @pnvm_loaded: indicates PNVM was loaded
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* @pm_support: set to true in start_hw if link pm is supported
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* @ltr_enabled: set to true if the LTR is enabled
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* @suppress_cmd_error_once: suppress "FW error in SYNC CMD" once,
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* e.g. for testing
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@ -884,7 +883,6 @@ struct iwl_trans {
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bool step_urm;
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bool suppress_cmd_error_once;
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bool pm_support;
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bool ltr_enabled;
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u8 pnvm_loaded:1;
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u8 fail_to_parse_pnvm_image:1;
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@ -1262,4 +1260,6 @@ static inline u16 iwl_trans_get_device_id(struct iwl_trans *trans)
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return u32_get_bits(trans->info.hw_id, GENMASK(31, 16));
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}
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bool iwl_trans_is_pm_supported(struct iwl_trans *trans);
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#endif /* __iwl_trans_h__ */
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@ -403,6 +403,7 @@ struct iwl_pcie_txqs {
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* @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
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* The user should use iwl_trans_{alloc,free}_tx_cmd.
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* @dev_cmd_pool_name: name for the TX command allocation pool
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* @pm_support: set to true in start_hw if link pm is supported
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*/
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struct iwl_trans_pcie {
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struct iwl_rxq *rxq;
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@ -512,6 +513,8 @@ struct iwl_trans_pcie {
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struct kmem_cache *dev_cmd_pool;
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char dev_cmd_pool_name[50];
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bool pm_support;
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};
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static inline struct iwl_trans_pcie *
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@ -1151,4 +1154,11 @@ int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
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int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
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struct iwl_trans_rxq_dma_data *data);
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static inline bool iwl_pcie_gen1_is_pm_supported(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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return trans_pcie->pm_support;
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}
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#endif /* __iwl_trans_int_pcie_h__ */
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@ -214,7 +214,7 @@ void iwl_pcie_apm_config(struct iwl_trans *trans)
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iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
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pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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trans_pcie->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
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trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
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