wifi: iwlwifi: pcie: move pm_support to the specific transport

Currently it is under iwl_trans, which is the bus agnostic part of the
transport. But really it is relevant for pcie only, so move it to the
iwl_trans_pcie and export it via an API to the opmode.

Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://patch.msgid.link/20250909061931.997193cabd04.Ic6648f040430c94150d0fa11601f50a6a630b862@changeid
This commit is contained in:
Miri Korenblit 2025-09-09 06:21:17 +03:00
parent da4234c0c4
commit 579c6a6e28
5 changed files with 23 additions and 4 deletions

View File

@ -368,7 +368,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
priv->power_data.bus_pm = priv->trans->pm_support;
priv->power_data.bus_pm = iwl_trans_is_pm_supported(priv->trans);
priv->power_data.debug_sleep_level_override = -1;

View File

@ -807,3 +807,12 @@ void iwl_trans_set_reduce_power(struct iwl_trans *trans,
{
iwl_trans_pcie_ctx_info_v2_set_reduce_power(trans, capa);
}
bool iwl_trans_is_pm_supported(struct iwl_trans *trans)
{
if (WARN_ON(trans->mac_cfg->gen2))
return false;
return iwl_pcie_gen1_is_pm_supported(trans);
}
IWL_EXPORT_SYMBOL(iwl_trans_is_pm_supported);

View File

@ -844,7 +844,6 @@ struct iwl_trans_info {
* @dev: pointer to struct device * that represents the device
* @info: device information for use by other layers
* @pnvm_loaded: indicates PNVM was loaded
* @pm_support: set to true in start_hw if link pm is supported
* @ltr_enabled: set to true if the LTR is enabled
* @suppress_cmd_error_once: suppress "FW error in SYNC CMD" once,
* e.g. for testing
@ -884,7 +883,6 @@ struct iwl_trans {
bool step_urm;
bool suppress_cmd_error_once;
bool pm_support;
bool ltr_enabled;
u8 pnvm_loaded:1;
u8 fail_to_parse_pnvm_image:1;
@ -1262,4 +1260,6 @@ static inline u16 iwl_trans_get_device_id(struct iwl_trans *trans)
return u32_get_bits(trans->info.hw_id, GENMASK(31, 16));
}
bool iwl_trans_is_pm_supported(struct iwl_trans *trans);
#endif /* __iwl_trans_h__ */

View File

@ -403,6 +403,7 @@ struct iwl_pcie_txqs {
* @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
* The user should use iwl_trans_{alloc,free}_tx_cmd.
* @dev_cmd_pool_name: name for the TX command allocation pool
* @pm_support: set to true in start_hw if link pm is supported
*/
struct iwl_trans_pcie {
struct iwl_rxq *rxq;
@ -512,6 +513,8 @@ struct iwl_trans_pcie {
struct kmem_cache *dev_cmd_pool;
char dev_cmd_pool_name[50];
bool pm_support;
};
static inline struct iwl_trans_pcie *
@ -1151,4 +1154,11 @@ int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
struct iwl_trans_rxq_dma_data *data);
static inline bool iwl_pcie_gen1_is_pm_supported(struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
return trans_pcie->pm_support;
}
#endif /* __iwl_trans_int_pcie_h__ */

View File

@ -214,7 +214,7 @@ void iwl_pcie_apm_config(struct iwl_trans *trans)
iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
trans_pcie->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;