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Qualcomm clock updates for v6.18

Browse Source 
Introduce Glymur global, display, rpmh, and tcsr clock controllers.
 Introduce the IPQ5424 APSS clock controller. Extend the MSM8916 global
 clock controller, to add support for MSM8937.
 
 Convert alpha PLL to determine_rate().
 
 Add missing resets in SC7280 display clock controller.
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Merge tag 'qcom-clk-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Introduce Qualcomm Glymur global, display, rpmh, and tcsr clock controllers
 - Introduce Qualcomm IPQ5424 APSS clock controller
 - Extend the Qualcomm MSM8916 global clock controller to add support for MSM8937
 - Convert QUalcomm alpha PLL to determine_rate() clk_ops
 - Add missing resets in Qualcomm SC7280 display clock controller

* tag 'qcom-clk-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits)
  clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment
  clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk
  clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8937
  dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller
  clk: qcom: Select the intended config in QCS_DISPCC_615
  clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register()
  clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
  clk: qcom: milos: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock Controller
  dt-bindings: clock: qcom: document the Glymur Global Clock Controller
  clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL
  clk: qcom: rpmh: Add support for Glymur rpmh clocks
  clk: qcom: Add TCSR clock driver for Glymur SoC
  dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs
  clk: qcom: dispcc-glymur: Add support for Display Clock Controller
  dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC
  clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks
  dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs
  ...
This commit is contained in:
Stephen Boyd 2025-09-21 08:48:49 -07:00
commit 575e9a62b8
50 changed files with 13162 additions and 153 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
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@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
- Sireesh Kodali <sireeshkodali@protonmail.com>
- Barnabas Czeman <barnabas.czeman@mainlining.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8953.
domains on MSM8937 or MSM8953.
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8917.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
properties:
compatible:
const: qcom,gcc-msm8953
enum:
- qcom,gcc-msm8937
- qcom,gcc-msm8953
clocks:
items:

98
Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml Normal file
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@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on GLYMUR
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the MDSS instances on GLYMUR SoC.
See also:
include/dt-bindings/clock/qcom,dispcc-glymur.h
properties:
compatible:
enum:
- qcom,glymur-dispcc
clocks:
items:
- description: Board CXO clock
- description: Board sleep clock
- description: DisplayPort 0 link clock
- description: DisplayPort 0 VCO div clock
- description: DisplayPort 1 link clock
- description: DisplayPort 1 VCO div clock
- description: DisplayPort 2 link clock
- description: DisplayPort 2 VCO div clock
- description: DisplayPort 3 link clock
- description: DisplayPort 3 VCO div clock
- description: DSI 0 PLL byte clock
- description: DSI 0 PLL DSI clock
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
- description: Standalone PHY 0 PLL link clock
- description: Standalone PHY 0 VCO div clock
- description: Standalone PHY 1 PLL link clock
- description: Standalone PHY 1 VCO div clock
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss_dp_phy0 0>,
<&mdss_dp_phy0 1>,
<&mdss_dp_phy1 0>,
<&mdss_dp_phy1 1>,
<&mdss_dp_phy2 0>,
<&mdss_dp_phy2 1>,
<&mdss_dp_phy3 0>,
<&mdss_dp_phy3 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_phy0_link 0>,
<&mdss_phy0_vco_div 0>,
<&mdss_phy1_link 1>,
<&mdss_phy1_vco_div 1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

121
Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml Normal file
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@ -0,0 +1,121 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Glymur SoC.
See also: include/dt-bindings/clock/qcom,glymur-gcc.h
properties:
compatible:
const: qcom,glymur-gcc
clocks:
items:
- description: Board XO source
- description: Board XO_A source
- description: Sleep clock source
- description: USB 0 Phy DP0 GMUX clock source
- description: USB 0 Phy DP1 GMUX clock source
- description: USB 0 Phy PCIE PIPEGMUX clock source
- description: USB 0 Phy PIPEGMUX clock source
- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
- description: USB 1 Phy DP0 GMUX 2 clock source
- description: USB 1 Phy DP1 GMUX 2 clock source
- description: USB 1 Phy PCIE PIPEGMUX clock source
- description: USB 1 Phy PIPEGMUX clock source
- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
- description: USB 2 Phy DP0 GMUX 2 clock source
- description: USB 2 Phy DP1 GMUX 2 clock source
- description: USB 2 Phy PCIE PIPEGMUX clock source
- description: USB 2 Phy PIPEGMUX clock source
- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
- description: PCIe 3a pipe clock
- description: PCIe 3b pipe clock
- description: PCIe 4 pipe clock
- description: PCIe 5 pipe clock
- description: PCIe 6 pipe clock
- description: QUSB4 0 PHY RX 0 clock source
- description: QUSB4 0 PHY RX 1 clock source
- description: QUSB4 1 PHY RX 0 clock source
- description: QUSB4 1 PHY RX 1 clock source
- description: QUSB4 2 PHY RX 0 clock source
- description: QUSB4 2 PHY RX 1 clock source
- description: UFS PHY RX Symbol 0 clock source
- description: UFS PHY RX Symbol 1 clock source
- description: UFS PHY TX Symbol 0 clock source
- description: USB3 PHY 0 pipe clock source
- description: USB3 PHY 1 pipe clock source
- description: USB3 PHY 2 pipe clock source
- description: USB3 UNI PHY pipe 0 clock source
- description: USB3 UNI PHY pipe 1 clock source
- description: USB4 PHY 0 pcie pipe clock source
- description: USB4 PHY 0 Max pipe clock source
- description: USB4 PHY 1 pcie pipe clock source
- description: USB4 PHY 1 Max pipe clock source
- description: USB4 PHY 2 pcie pipe clock source
- description: USB4 PHY 2 Max pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,glymur-gcc";
reg = <0x100000 0x1f9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&usb_0_phy_dp0_gmux>,
<&usb_0_phy_dp1_gmux>,
<&usb_0_phy_pcie_pipegmux>,
<&usb_0_phy_pipegmux>,
<&usb_0_phy_sys_pcie_pipegmux>,
<&usb_1_phy_dp0_gmux_2>,
<&usb_1_phy_dp1_gmux_2>,
<&usb_1_phy_pcie_pipegmux>,
<&usb_1_phy_pipegmux>,
<&usb_1_phy_sys_pcie_pipegmux>,
<&usb_2_phy_dp0_gmux 2>,
<&usb_2_phy_dp1_gmux 2>,
<&usb_2_phy_pcie_pipegmux>,
<&usb_2_phy_pipegmux>,
<&usb_2_phy_sys_pcie_pipegmux>,
<&pcie_3a_pipe>, <&pcie_3b_pipe>,
<&pcie_4_pipe>, <&pcie_5_pipe>,
<&pcie_6_pipe>,
<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
<&ufs_phy_tx_symbol_0>,
<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
<&usb3_phy_2_pipe>,
<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

55
Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APSS IPQ5424 Clock Controller
maintainers:
- Varadarajan Narayanan <quic_varada@quicinc.com>
description:
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
properties:
compatible:
enum:
- qcom,ipq5424-apss-clk
reg:
maxItems: 1
clocks:
items:
- description: Reference to the XO clock.
- description: Reference to the GPLL0 clock.
'#clock-cells':
const: 1
'#interconnect-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#interconnect-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
apss_clk: clock-controller@fa80000 {
compatible = "qcom,ipq5424-apss-clk";
reg = <0x0fa80000 0x20000>;
clocks = <&xo_board>,
<&gcc GPLL0>;
#clock-cells = <1>;
#interconnect-cells = <1>;
};

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,glymur-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk

3
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@ -22,6 +24,7 @@ properties:
compatible:
items:
- enum:
- qcom,glymur-tcsr
- qcom,milos-tcsr
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr

23
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
View File

@ -23,13 +23,17 @@ description: |
properties:
compatible:
enum:
- qcom,sc7180-videocc
- qcom,sc7280-videocc
- qcom,sdm845-videocc
- qcom,sm6350-videocc
- qcom,sm8150-videocc
- qcom,sm8250-videocc
oneOf:
- enum:
- qcom,sc7180-videocc
- qcom,sc7280-videocc
- qcom,sdm845-videocc
- qcom,sm6350-videocc
- qcom,sm8150-videocc
- qcom,sm8250-videocc
- items:
- const: qcom,sc8180x-videocc
- const: qcom,sm8150-videocc
clocks:
minItems: 1
@ -110,8 +114,9 @@ allOf:
- if:
properties:
compatible:
enum:
- qcom,sm8150-videocc
contains:
enum:
- qcom,sm8150-videocc
then:
properties:
clocks:

44
drivers/clk/qcom/Kconfig
View File

@ -19,6 +19,33 @@ menuconfig COMMON_CLK_QCOM
if COMMON_CLK_QCOM
config CLK_GLYMUR_DISPCC
tristate "GLYMUR Display Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_GLYMUR_GCC
help
Support for the display clock controllers on Qualcomm
Technologies, Inc. GLYMUR devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config CLK_GLYMUR_GCC
tristate "GLYMUR Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on GLYMUR devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
config CLK_GLYMUR_TCSRCC
tristate "GLYMUR TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the TCSR clock controller on GLYMUR devices.
Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
config CLK_X1E80100_CAMCC
tristate "X1E80100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -187,6 +214,15 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
config IPQ_APSS_5424
tristate "IPQ APSS Clock Controller"
select IPQ_APSS_PLL
default y if IPQ_GCC_5424
help
Support for APSS Clock controller on Qualcom IPQ5424 platform.
Say Y if you want to support CPU frequency scaling on ipq based
devices.
config IPQ_APSS_6018
tristate "IPQ APSS Clock Controller"
select IPQ_APSS_PLL
@ -323,12 +359,12 @@ config MSM_GCC_8916
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8917
tristate "MSM8917/QM215 Global Clock Controller"
tristate "MSM89(17/37)/QM215 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on msm8917 and qm215
devices.
Support for the global clock controller on msm8917, msm8937
and qm215 devices.
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
@ -495,7 +531,7 @@ config QCM_DISPCC_2290
config QCS_DISPCC_615
tristate "QCS615 Display Clock Controller"
select QCM_GCC_615
select QCS_GCC_615
help
Support for the display clock controller on Qualcomm Technologies, Inc
QCS615 devices.

4
drivers/clk/qcom/Makefile
View File

@ -21,6 +21,9 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
@ -29,6 +32,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o
obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_5424) += apss-ipq5424.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o

2
drivers/clk/qcom/a7-pll.c
View File

@ -27,7 +27,7 @@ static struct clk_alpha_pll a7pll = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "a7pll",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,

265
drivers/clk/qcom/apss-ipq5424.c Normal file
View File

@ -0,0 +1,265 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interconnect/qcom,ipq5424.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
enum {
DT_XO,
DT_CLK_REF,
};
enum {
P_XO,
P_GPLL0,
P_APSS_PLL_EARLY,
P_L3_PLL,
};
struct apss_clk {
struct notifier_block cpu_clk_notifier;
struct clk_hw *hw;
struct device *dev;
struct clk *l3_clk;
};
static const struct alpha_pll_config apss_pll_config = {
.l = 0x3b,
.config_ctl_val = 0x08200920,
.config_ctl_hi_val = 0x05008001,
.config_ctl_hi1_val = 0x04000000,
.user_ctl_val = 0xf,
};
static struct clk_alpha_pll ipq5424_apss_pll = {
.offset = 0x0,
.config = &apss_pll_config,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "apss_pll",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
},
};
static const struct clk_parent_data parents_apss_silver_clk_src[] = {
{ .index = DT_XO },
{ .index = DT_CLK_REF },
{ .hw = &ipq5424_apss_pll.clkr.hw },
};
static const struct parent_map parents_apss_silver_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 4 },
{ P_APSS_PLL_EARLY, 5 },
};
static const struct freq_tbl ftbl_apss_clk_src[] = {
F(816000000, P_APSS_PLL_EARLY, 1, 0, 0),
F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0),
F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0),
{ }
};
static struct clk_rcg2 apss_silver_clk_src = {
.cmd_rcgr = 0x0080,
.freq_tbl = ftbl_apss_clk_src,
.hid_width = 5,
.parent_map = parents_apss_silver_clk_src_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apss_silver_clk_src",
.parent_data = parents_apss_silver_clk_src,
.num_parents = ARRAY_SIZE(parents_apss_silver_clk_src),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch apss_silver_core_clk = {
.halt_reg = 0x008c,
.clkr = {
.enable_reg = 0x008c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "apss_silver_core_clk",
.parent_hws = (const struct clk_hw *[]) {
&apss_silver_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static const struct alpha_pll_config l3_pll_config = {
.l = 0x29,
.config_ctl_val = 0x08200920,
.config_ctl_hi_val = 0x05008001,
.config_ctl_hi1_val = 0x04000000,
.user_ctl_val = 0xf,
};
static struct clk_alpha_pll ipq5424_l3_pll = {
.offset = 0x10000,
.config = &l3_pll_config,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "l3_pll",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
},
};
static const struct clk_parent_data parents_l3_clk_src[] = {
{ .index = DT_XO },
{ .index = DT_CLK_REF },
{ .hw = &ipq5424_l3_pll.clkr.hw },
};
static const struct parent_map parents_l3_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 4 },
{ P_L3_PLL, 5 },
};
static const struct freq_tbl ftbl_l3_clk_src[] = {
F(816000000, P_L3_PLL, 1, 0, 0),
F(984000000, P_L3_PLL, 1, 0, 0),
F(1272000000, P_L3_PLL, 1, 0, 0),
{ }
};
static struct clk_rcg2 l3_clk_src = {
.cmd_rcgr = 0x10080,
.freq_tbl = ftbl_l3_clk_src,
.hid_width = 5,
.parent_map = parents_l3_clk_src_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "l3_clk_src",
.parent_data = parents_l3_clk_src,
.num_parents = ARRAY_SIZE(parents_l3_clk_src),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch l3_core_clk = {
.halt_reg = 0x1008c,
.clkr = {
.enable_reg = 0x1008c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "l3_clk",
.parent_hws = (const struct clk_hw *[]) {
&l3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static const struct regmap_config apss_ipq5424_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x20000,
.fast_io = true,
};
static struct clk_regmap *apss_ipq5424_clks[] = {
[APSS_PLL_EARLY] = &ipq5424_apss_pll.clkr,
[APSS_SILVER_CLK_SRC] = &apss_silver_clk_src.clkr,
[APSS_SILVER_CORE_CLK] = &apss_silver_core_clk.clkr,
[L3_PLL] = &ipq5424_l3_pll.clkr,
[L3_CLK_SRC] = &l3_clk_src.clkr,
[L3_CORE_CLK] = &l3_core_clk.clkr,
};
static struct clk_alpha_pll *ipa5424_apss_plls[] = {
&ipq5424_l3_pll,
&ipq5424_apss_pll,
};
static struct qcom_cc_driver_data ipa5424_apss_driver_data = {
.alpha_plls = ipa5424_apss_plls,
.num_alpha_plls = ARRAY_SIZE(ipa5424_apss_plls),
};
#define IPQ_APPS_PLL_ID (5424 * 3) /* some unique value */
static const struct qcom_icc_hws_data icc_ipq5424_cpu_l3[] = {
{ MASTER_CPU, SLAVE_L3, L3_CORE_CLK },
};
static const struct qcom_cc_desc apss_ipq5424_desc = {
.config = &apss_ipq5424_regmap_config,
.clks = apss_ipq5424_clks,
.num_clks = ARRAY_SIZE(apss_ipq5424_clks),
.icc_hws = icc_ipq5424_cpu_l3,
.num_icc_hws = ARRAY_SIZE(icc_ipq5424_cpu_l3),
.icc_first_node_id = IPQ_APPS_PLL_ID,
.driver_data = &ipa5424_apss_driver_data,
};
static int apss_ipq5424_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &apss_ipq5424_desc);
}
static const struct of_device_id apss_ipq5424_match_table[] = {
{ .compatible = "qcom,ipq5424-apss-clk" },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq5424_match_table);
static struct platform_driver apss_ipq5424_driver = {
.probe = apss_ipq5424_probe,
.driver = {
.name = "apss-ipq5424-clk",
.of_match_table = apss_ipq5424_match_table,
.sync_state = icc_sync_state,
},
};
module_platform_driver(apss_ipq5424_driver);
MODULE_DESCRIPTION("QCOM APSS IPQ5424 CLK Driver");
MODULE_LICENSE("GPL");

2
drivers/clk/qcom/camcc-milos.c
View File

@ -2124,7 +2124,7 @@ static struct qcom_cc_driver_data cam_cc_milos_driver_data = {
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_milos_critical_cbcrs),
};
static struct qcom_cc_desc cam_cc_milos_desc = {
static const struct qcom_cc_desc cam_cc_milos_desc = {
.config = &cam_cc_milos_regmap_config,
.clks = cam_cc_milos_clocks,
.num_clks = ARRAY_SIZE(cam_cc_milos_clocks),

162
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -66,7 +66,7 @@
#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS)
const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
@ -77,7 +77,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x10,
@ -87,7 +87,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
@ -97,7 +97,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
@ -110,7 +110,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_OPMODE] = 0x28,
[PLL_OFF_STATUS] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
@ -119,7 +119,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
@ -147,7 +147,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_ALPHA_VAL] = 0x40,
},
[CLK_ALPHA_PLL_TYPE_AGERA] = {
[CLK_ALPHA_PLL_TYPE_AGERA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
@ -157,7 +157,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x1c,
[PLL_OFF_STATUS] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
@ -243,7 +243,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
@ -254,7 +254,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
@ -275,7 +275,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_USER_CTL] = 0x08,
[PLL_OFF_USER_CTL_U] = 0x0c,
@ -286,7 +286,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
@ -301,7 +301,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_OPMODE] = 0x30,
[PLL_OFF_STATUS] = 0x3c,
},
[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_TEST_CTL] = 0x0c,
@ -849,22 +849,25 @@ static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
clk_alpha_pll_hwfsm_is_enabled);
}
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_alpha_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
unsigned long min_freq, max_freq;
rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
&a, alpha_width);
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
return 0;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
req->rate = clamp(req->rate, min_freq, max_freq);
return 0;
}
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@ -1048,12 +1051,15 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
u32 l, a;
return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
req->rate = alpha_huayra_pll_round_rate(req->rate,
req->best_parent_rate, &l, &a);
return 0;
}
static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@ -1175,7 +1181,7 @@ const struct clk_ops clk_alpha_pll_ops = {
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_alpha_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
@ -1185,7 +1191,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = {
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_huayra_recalc_rate,
.round_rate = alpha_pll_huayra_round_rate,
.determine_rate = alpha_pll_huayra_determine_rate,
.set_rate = alpha_pll_huayra_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
@ -1195,7 +1201,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
.disable = clk_alpha_pll_hwfsm_disable,
.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_alpha_pll_hwfsm_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@ -1205,7 +1211,7 @@ const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
@ -1240,9 +1246,8 @@ static const struct clk_div_table clk_alpha_2bit_div_table[] = {
{ }
};
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
const struct clk_div_table *table;
@ -1252,13 +1257,15 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
else
table = clk_alpha_div_table;
return divider_round_rate(hw, rate, prate, table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
table, pll->width,
CLK_DIVIDER_POWER_OF_TWO);
return 0;
}
static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl, div;
@ -1270,9 +1277,12 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
div = 1 << fls(ctl);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
div * req->rate);
return DIV_ROUND_UP_ULL((u64)*prate, div);
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
return 0;
}
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
@ -1291,13 +1301,13 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
const struct clk_ops clk_alpha_pll_postdiv_ops = {
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_round_rate,
.determine_rate = clk_alpha_pll_postdiv_determine_rate,
.set_rate = clk_alpha_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
.round_rate = clk_alpha_pll_postdiv_round_ro_rate,
.determine_rate = clk_alpha_pll_postdiv_ro_determine_rate,
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
@ -1542,7 +1552,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops = {
.is_enabled = clk_alpha_pll_is_enabled,
.set_rate = alpha_pll_fabia_set_rate,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
@ -1551,7 +1561,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
.disable = alpha_pll_fabia_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
@ -1602,14 +1612,16 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
return (parent_rate / div);
}
static long
clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
return divider_round_rate(hw, rate, prate, pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
return 0;
};
static int
@ -1635,18 +1647,21 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
.round_rate = clk_trion_pll_postdiv_round_rate,
.determine_rate = clk_trion_pll_postdiv_determine_rate,
.set_rate = clk_trion_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *prate)
static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
return divider_round_rate(hw, rate, prate, pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
return 0;
}
static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
@ -1681,7 +1696,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
@ -1833,7 +1848,7 @@ const struct clk_ops clk_alpha_pll_trion_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = alpha_pll_trion_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
@ -1844,14 +1859,14 @@ const struct clk_ops clk_alpha_pll_lucid_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = alpha_pll_trion_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
@ -1903,7 +1918,7 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_alpha_pll_agera_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
@ -2119,7 +2134,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
@ -2129,13 +2144,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
@ -2304,7 +2319,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
.disable = clk_zonda_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
@ -2529,13 +2544,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
.disable = alpha_pll_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
@ -2546,7 +2561,7 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
.disable = alpha_pll_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
@ -2557,7 +2572,7 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
.disable = alpha_pll_reset_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
@ -2732,22 +2747,25 @@ static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
return parent_rate * l;
}
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long min_freq, max_freq;
u32 l;
u64 a;
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
&a, 0);
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
return 0;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
req->rate = clamp(req->rate, min_freq, max_freq);
return 0;
}
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
@ -2755,7 +2773,7 @@ const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
.round_rate = clk_rivian_evo_pll_round_rate,
.determine_rate = clk_rivian_evo_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
@ -2964,7 +2982,7 @@ const struct clk_ops clk_alpha_pll_regera_ops = {
.disable = clk_zonda_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
@ -3169,7 +3187,7 @@ const struct clk_ops clk_alpha_pll_slew_ops = {
.enable = clk_alpha_pll_slew_enable,
.disable = clk_alpha_pll_disable,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.determine_rate = clk_alpha_pll_determine_rate,
.set_rate = clk_alpha_pll_slew_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_slew_ops);

6
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -29,6 +29,7 @@ enum {
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_PONGO_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
@ -192,14 +193,17 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops
#define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops
#define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops
#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_pongo_elu_ops;
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
@ -233,6 +237,8 @@ void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
const struct alpha_pll_config *config);
#define clk_taycan_elu_pll_configure(pll, regmap, config) \
clk_lucid_evo_pll_configure(pll, regmap, config)
#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \
clk_lucid_evo_pll_configure(pll, regmap, config)
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);

2
drivers/clk/qcom/clk-rcg.c
View File

@ -423,7 +423,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;
req->best_parent_rate = rate;

8
drivers/clk/qcom/clk-rcg2.c
View File

@ -201,7 +201,7 @@ __clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
m &= mask;
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
n = ~n;
n = ~n;
n &= mask;
n += m;
mode = cfg & CFG_MODE_MASK;
@ -274,7 +274,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;
req->best_parent_rate = rate;
@ -311,7 +311,7 @@ __clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f,
if (!p)
continue;
parent_rate = clk_hw_get_rate(p);
parent_rate = clk_hw_get_rate(p);
rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
if (rate == req_rate) {
@ -382,7 +382,7 @@ static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_mult
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;

28
drivers/clk/qcom/clk-rpmh.c
View File

@ -87,7 +87,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
@ -105,7 +105,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
.name = #_name "_ao", \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
@ -182,7 +182,7 @@ static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
}
c->last_sent_aggr_state = c->aggr_state;
c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
return 0;
}
@ -390,6 +390,11 @@ DEFINE_CLK_RPMH_VRM(clk7, _a4, "clka7", 4);
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_VRM(clk3, _a, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
DEFINE_CLK_RPMH_BCM(ipa, "IP0");
@ -879,6 +884,22 @@ static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
.clka_optional = true,
};
static struct clk_hw *glymur_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_glymur = {
.clks = glymur_rpmh_clocks,
.num_clks = ARRAY_SIZE(glymur_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -968,6 +989,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
{ .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},

8
drivers/clk/qcom/clk-smd-rpm.c
View File

@ -30,7 +30,7 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
@ -47,7 +47,7 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_active, \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
@ -74,7 +74,7 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
@ -92,7 +92,7 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_active, \
.parent_data = &(const struct clk_parent_data){ \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \

4
drivers/clk/qcom/common.c
View File

@ -277,8 +277,8 @@ static int qcom_cc_icc_register(struct device *dev,
icd[i].slave_id = desc->icc_hws[i].slave_id;
hws = &desc->clks[desc->icc_hws[i].clk_id]->hw;
icd[i].clk = devm_clk_hw_get_clk(dev, hws, "icc");
if (!icd[i].clk)
return dev_err_probe(dev, -ENOENT,
if (IS_ERR(icd[i].clk))
return dev_err_probe(dev, PTR_ERR(icd[i].clk),
"(%d) clock entry is null\n", i);
icd[i].name = clk_hw_get_name(hws);
}

1982
drivers/clk/qcom/dispcc-glymur.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/clk/qcom/dispcc-milos.c
View File

@ -937,7 +937,7 @@ static struct qcom_cc_driver_data disp_cc_milos_driver_data = {
.clk_regs_configure = disp_cc_milos_clk_regs_configure,
};
static struct qcom_cc_desc disp_cc_milos_desc = {
static const struct qcom_cc_desc disp_cc_milos_desc = {
.config = &disp_cc_milos_regmap_config,
.clks = disp_cc_milos_clocks,
.num_clks = ARRAY_SIZE(disp_cc_milos_clocks),

8
drivers/clk/qcom/dispcc-sc7280.c
View File

@ -17,6 +17,7 @@
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
@ -847,6 +848,11 @@ static struct gdsc *disp_cc_sc7280_gdscs[] = {
[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
};
static const struct qcom_reset_map disp_cc_sc7280_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
};
static const struct regmap_config disp_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -861,6 +867,8 @@ static const struct qcom_cc_desc disp_cc_sc7280_desc = {
.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
.gdscs = disp_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
.resets = disp_cc_sc7280_resets,
.num_resets = ARRAY_SIZE(disp_cc_sc7280_resets),
};
static const struct of_device_id disp_cc_sc7280_match_table[] = {

8616
drivers/clk/qcom/gcc-glymur.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
drivers/clk/qcom/gcc-ipq6018.c
View File

@ -511,15 +511,23 @@ static struct clk_rcg2 apss_ahb_clk_src = {
},
};
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
C(P_UNIPHY1_RX, 12.5, 0, 0),
C(P_UNIPHY0_RX, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
C(P_UNIPHY1_RX, 2.5, 0, 0),
C(P_UNIPHY0_RX, 1, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
FMS(24000000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port5_rx_clk_src_25),
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
FM(125000000, ftbl_nss_port5_rx_clk_src_125),
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
};
@ -547,26 +555,34 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
.num_parents = 7,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
C(P_UNIPHY1_TX, 12.5, 0, 0),
C(P_UNIPHY0_TX, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
C(P_UNIPHY1_TX, 2.5, 0, 0),
C(P_UNIPHY0_TX, 1, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
FMS(24000000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port5_tx_clk_src_25),
FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
FM(125000000, ftbl_nss_port5_tx_clk_src_125),
FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
};
@ -594,14 +610,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
.num_parents = 7,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};

617
drivers/clk/qcom/gcc-msm8917.c
View File

@ -37,6 +37,8 @@ enum {
DT_SLEEP_CLK,
DT_DSI0PLL,
DT_DSI0PLL_BYTE,
DT_DSI1PLL,
DT_DSI1PLL_BYTE,
};
enum {
@ -48,6 +50,8 @@ enum {
P_GPLL6,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL,
P_DSI1PLL_BYTE,
};
static struct clk_alpha_pll gpll0_sleep_clk_src = {
@ -102,7 +106,11 @@ static const struct pll_vco gpll3_p_vco[] = {
{ 700000000, 1400000000, 0 },
};
static const struct alpha_pll_config gpll3_early_config = {
static const struct pll_vco gpll3_p_vco_msm8937[] = {
{ 525000000, 1066000000, 0 },
};
static struct alpha_pll_config gpll3_early_config = {
.l = 63,
.config_ctl_val = 0x4001055b,
.early_output_mask = 0,
@ -273,6 +281,19 @@ static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
@ -351,6 +372,19 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
}
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x18000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
@ -362,6 +396,20 @@ static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.hid_width = 5,
@ -446,6 +494,20 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
}
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x18024,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
@ -525,11 +587,19 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
static const struct parent_map gcc_byte0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 3 },
};
static const struct parent_map gcc_byte1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 3 },
{ P_DSI1PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_byte_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL_BYTE },
{ .index = DT_DSI1PLL_BYTE },
};
static struct clk_rcg2 byte0_clk_src = {
@ -545,6 +615,19 @@ static struct clk_rcg2 byte0_clk_src = {
}
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x4d0b0,
.hid_width = 5,
.parent_map = gcc_byte1_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = gcc_byte_data,
.num_parents = ARRAY_SIZE(gcc_byte_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
@ -642,6 +725,17 @@ static const struct freq_tbl ftbl_cpp_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_cpp_clk_src_msm8937[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 5, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
@ -655,6 +749,13 @@ static struct clk_rcg2 cpp_clk_src = {
}
};
static struct clk_init_data vcodec0_clk_src_init_msm8937 = {
.name = "vcodec0_clk_src",
.parent_data = gcc_cpp_data,
.num_parents = ARRAY_SIZE(gcc_cpp_data),
.ops = &clk_rcg2_ops,
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
@ -730,6 +831,13 @@ static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_csi_phytimer_clk_src_msm8937[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
@ -774,6 +882,19 @@ static struct clk_rcg2 esc0_clk_src = {
}
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x4d0a8,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_xo_gpll0_out_aux_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static const struct parent_map gcc_gfx3d_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
@ -817,6 +938,25 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(216000000, P_GPLL6, 5, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(240000000, P_GPLL6, 4.5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(300000000, P_GPLL3, 1, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(375000000, P_GPLL3, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(450000000, P_GPLL3, 1, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
@ -973,21 +1113,29 @@ static struct clk_rcg2 mdp_clk_src = {
}
};
static const struct parent_map gcc_pclk_map[] = {
static const struct parent_map gcc_pclk0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 3 },
};
static const struct parent_map gcc_pclk1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 3 },
{ P_DSI1PLL, 1 },
};
static const struct clk_parent_data gcc_pclk_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL },
{ .index = DT_DSI1PLL },
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk_map,
.parent_map = gcc_pclk0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pclk0_clk_src",
.parent_data = gcc_pclk_data,
@ -997,6 +1145,20 @@ static struct clk_rcg2 pclk0_clk_src = {
}
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x4d0b8,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk1_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = gcc_pclk_data,
.num_parents = ARRAY_SIZE(gcc_pclk_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
@ -1108,6 +1270,14 @@ static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_usb_hs_system_clk_src_msm8937[] = {
F(57142857, P_GPLL0, 14, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
@ -1132,6 +1302,15 @@ static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_vcodec0_clk_src_msm8937[] = {
F(166150000, P_GPLL6, 6.5, 0, 0),
F(240000000, P_GPLL6, 4.5, 0, 0),
F(308571428, P_GPLL6, 3.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.hid_width = 5,
@ -1160,6 +1339,23 @@ static const struct freq_tbl ftbl_vfe_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_vfe_clk_src_msm8937[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
F(308571428, P_GPLL6, 3.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(432000000, P_GPLL6, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
@ -1269,6 +1465,24 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
}
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.halt_check = BRANCH_HALT,
@ -1377,6 +1591,42 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
}
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x18020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x18020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.halt_check = BRANCH_HALT,
@ -1485,6 +1735,24 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
}
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x1801c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1801c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.halt_check = BRANCH_HALT,
@ -2521,6 +2789,24 @@ static struct clk_branch gcc_mdss_byte0_clk = {
}
};
static struct clk_branch gcc_mdss_byte1_clk = {
.halt_reg = 0x4d0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
@ -2539,6 +2825,24 @@ static struct clk_branch gcc_mdss_esc0_clk = {
}
};
static struct clk_branch gcc_mdss_esc1_clk = {
.halt_reg = 0x4d09c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d09c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
@ -2575,6 +2879,24 @@ static struct clk_branch gcc_mdss_pclk0_clk = {
}
};
static struct clk_branch gcc_mdss_pclk1_clk = {
.halt_reg = 0x4d0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
@ -2632,6 +2954,24 @@ static struct clk_branch gcc_oxili_ahb_clk = {
}
};
static struct clk_branch gcc_oxili_aon_clk = {
.halt_reg = 0x5904c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5904c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.halt_check = BRANCH_HALT,
@ -2650,6 +2990,19 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
}
};
static struct clk_branch gcc_oxili_timer_clk = {
.halt_reg = 0x59040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_timer_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
@ -3027,6 +3380,28 @@ static struct gdsc oxili_gx_gdsc = {
.flags = CLAMP_IO,
};
static struct gdsc oxili_gx_gdsc_msm8937 = {
.gdscr = 0x5901c,
.clamp_io_ctrl = 0x5b00c,
.cxcs = (unsigned int []){ 0x59000 },
.cxc_count = 1,
.pd = {
.name = "oxili_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO,
};
static struct gdsc oxili_cx_gdsc = {
.gdscr = 0x59044,
.cxcs = (unsigned int []){ 0x59020 },
.cxc_count = 1,
.pd = {
.name = "oxili_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x58078,
.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
@ -3207,6 +3582,188 @@ static struct clk_regmap *gcc_msm8917_clocks[] = {
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
};
static struct clk_regmap *gcc_msm8937_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_EARLY] = &gpll3_early.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL6] = &gpll6,
[GPLL6_EARLY] = &gpll6_early.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[MSM8937_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[MSM8937_ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[MSM8937_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[MSM8937_GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[MSM8937_GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[MSM8937_GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[MSM8937_GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[MSM8937_GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8917_resets[] = {
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
[GCC_MSS_BCR] = { 0x71000 },
@ -3234,6 +3791,18 @@ static struct gdsc *gcc_msm8917_gdscs[] = {
[VFE1_GDSC] = &vfe1_gdsc,
};
static struct gdsc *gcc_msm8937_gdscs[] = {
[CPP_GDSC] = &cpp_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[OXILI_GX_GDSC] = &oxili_gx_gdsc_msm8937,
[MSM8937_OXILI_CX_GDSC] = &oxili_cx_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VFE0_GDSC] = &vfe0_gdsc,
[VFE1_GDSC] = &vfe1_gdsc,
};
static const struct qcom_cc_desc gcc_msm8917_desc = {
.config = &gcc_msm8917_regmap_config,
.clks = gcc_msm8917_clocks,
@ -3254,6 +3823,41 @@ static const struct qcom_cc_desc gcc_qm215_desc = {
.num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
};
static const struct qcom_cc_desc gcc_msm8937_desc = {
.config = &gcc_msm8917_regmap_config,
.clks = gcc_msm8937_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8937_clocks),
.resets = gcc_msm8917_resets,
.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
.gdscs = gcc_msm8937_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
};
static void msm8937_clock_override(void)
{
/* GPLL3 750MHz configuration */
gpll3_early_config.l = 47;
gpll3_early.vco_table = gpll3_p_vco_msm8937;
gpll3_early.num_vco = ARRAY_SIZE(gpll3_p_vco_msm8937);
/*
* Set below clocks for use specific msm8937 parent map.
*/
vcodec0_clk_src.parent_map = gcc_cpp_map;
vcodec0_clk_src.clkr.hw.init = &vcodec0_clk_src_init_msm8937;
/*
* Set below clocks for use specific msm8937 freq table.
*/
vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_msm8937;
vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_msm8937;
csi0phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
csi1phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_msm8937;
}
static int gcc_msm8917_probe(struct platform_device *pdev)
{
struct regmap *regmap;
@ -3261,8 +3865,12 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
gcc_desc = of_device_get_match_data(&pdev->dev);
if (gcc_desc == &gcc_qm215_desc)
if (gcc_desc == &gcc_qm215_desc) {
gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215;
} else if (gcc_desc == &gcc_msm8937_desc) {
msm8937_clock_override();
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937;
}
regmap = qcom_cc_map(pdev, gcc_desc);
if (IS_ERR(regmap))
@ -3276,6 +3884,7 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
static const struct of_device_id gcc_msm8917_match_table[] = {
{ .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
{ .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
{},
};
MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);

2
drivers/clk/qcom/gcc-qcs404.c
View File

@ -2754,7 +2754,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
};

4
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -6775,10 +6775,6 @@ static struct gdsc pcie_1_tunnel_gdsc = {
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
/*
* The Qualcomm PCIe driver does not yet implement suspend so to keep the
* PCIe power domains always-on for now.
*/
static struct gdsc pcie_2a_gdsc = {
.gdscr = 0x9d004,
.collapse_ctrl = 0x52128,

72
drivers/clk/qcom/gcc-sdm660.c
View File

@ -2247,6 +2247,45 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
},
};
static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
.halt_reg = 0x7d014,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7d014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "hlos1_vote_lpass_adsp_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {
.halt_reg = 0x7d048,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7d048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "hlos1_vote_turing_adsp_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = {
.halt_reg = 0x7e048,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7e048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "hlos2_vote_turing_adsp_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc ufs_gdsc = {
.gdscr = 0x75004,
.gds_hw_ctrl = 0x0,
@ -2277,6 +2316,33 @@ static struct gdsc pcie_0_gdsc = {
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_adsp_gdsc = {
.gdscr = 0x7d04c,
.pd = {
.name = "hlos1_vote_turing_adsp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos2_vote_turing_adsp_gdsc = {
.gdscr = 0x7e04c,
.pd = {
.name = "hlos2_vote_turing_adsp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
.gdscr = 0x7d034,
.pd = {
.name = "hlos1_vote_lpass_adsp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_hw *gcc_sdm660_hws[] = {
&xo.hw,
&gpll0_early_div.hw,
@ -2409,12 +2475,18 @@ static struct clk_regmap *gcc_sdm660_clocks[] = {
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
[GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr,
[GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = &hlos1_vote_turing_adsp_smmu_clk.clkr,
[GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = &hlos2_vote_turing_adsp_smmu_clk.clkr,
};
static struct gdsc *gcc_sdm660_gdscs[] = {
[UFS_GDSC] = &ufs_gdsc,
[USB_30_GDSC] = &usb_30_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
[HLOS1_VOTE_TURING_ADSP_GDSC] = &hlos1_vote_turing_adsp_gdsc,
[HLOS2_VOTE_TURING_ADSP_GDSC] = &hlos2_vote_turing_adsp_gdsc,
[HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
};
static const struct qcom_reset_map gcc_sdm660_resets[] = {

6
drivers/clk/qcom/gpucc-sa8775p.c
View File

@ -365,7 +365,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
@ -414,7 +414,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -499,7 +499,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = {
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},

2
drivers/clk/qcom/gpucc-sc7180.c
View File

@ -42,7 +42,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,

4
drivers/clk/qcom/gpucc-sm6350.c
View File

@ -67,7 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
@ -111,7 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},

2
drivers/clk/qcom/gpucc-sm8150.c
View File

@ -53,7 +53,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,

2
drivers/clk/qcom/gpucc-sm8250.c
View File

@ -56,7 +56,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,

4
drivers/clk/qcom/lpassaudiocc-sc7280.c
View File

@ -709,8 +709,8 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
};
static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
};

4
drivers/clk/qcom/lpasscc-sc8280xp.c
View File

@ -18,9 +18,9 @@
#include "reset.h"
static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
};
static const struct regmap_config lpass_audiocc_sc8280xp_regmap_config = {

2
drivers/clk/qcom/lpasscc-sm6115.c
View File

@ -17,7 +17,7 @@
#include "reset.h"
static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { .reg = 0x98, .bit = 1, .udelay = 500 },
[LPASS_AUDIO_SWR_RX_CGCR] = { .reg = 0x98, .bit = 1, .udelay = 500 },
};
static struct regmap_config lpass_audiocc_sm6115_regmap_config = {

2
drivers/clk/qcom/lpasscorecc-sc7180.c
View File

@ -42,7 +42,7 @@ static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
};
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_CAL_L_VAL] = 0x8,
[PLL_OFF_USER_CTL] = 0x0c,

2
drivers/clk/qcom/mmcc-sdm660.c
View File

@ -74,7 +74,7 @@ static struct clk_alpha_pll mmpll0 = {
},
};
static struct clk_alpha_pll mmpll6 = {
static struct clk_alpha_pll mmpll6 = {
.offset = 0xf0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {

2
drivers/clk/qcom/nsscc-ipq9574.c
View File

@ -3016,7 +3016,7 @@ static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
[NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },
[NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },
[NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },
[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
};
static const struct regmap_config nss_cc_ipq9574_regmap_config = {

313
drivers/clk/qcom/tcsrcc-glymur.c Normal file
View File

@ -0,0 +1,313 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
};
static struct clk_branch tcsr_edp_clkref_en = {
.halt_reg = 0x1c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_2_clkref_en = {
.halt_reg = 0x8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_3_clkref_en = {
.halt_reg = 0x10,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_4_clkref_en = {
.halt_reg = 0x14,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x14,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
.halt_reg = 0x28,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x28,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
.halt_reg = 0x2c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_3_clkref_en = {
.halt_reg = 0x30,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x30,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_4_clkref_en = {
.halt_reg = 0x44,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x44,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_0_clkref_en = {
.halt_reg = 0x20,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_1_clkref_en = {
.halt_reg = 0x24,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x24,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
.halt_reg = 0x0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
.halt_reg = 0x18,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x18,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_glymur_clocks[] = {
[TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_PCIE_2_CLKREF_EN] = &tcsr_pcie_2_clkref_en.clkr,
[TCSR_PCIE_3_CLKREF_EN] = &tcsr_pcie_3_clkref_en.clkr,
[TCSR_PCIE_4_CLKREF_EN] = &tcsr_pcie_4_clkref_en.clkr,
[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
[TCSR_USB2_3_CLKREF_EN] = &tcsr_usb2_3_clkref_en.clkr,
[TCSR_USB2_4_CLKREF_EN] = &tcsr_usb2_4_clkref_en.clkr,
[TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
[TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
[TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
[TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
};
static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x44,
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_glymur_desc = {
.config = &tcsr_cc_glymur_regmap_config,
.clks = tcsr_cc_glymur_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_glymur_clocks),
};
static const struct of_device_id tcsr_cc_glymur_match_table[] = {
{ .compatible = "qcom,glymur-tcsr" },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table);
static int tcsr_cc_glymur_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc);
}
static struct platform_driver tcsr_cc_glymur_driver = {
.probe = tcsr_cc_glymur_probe,
.driver = {
.name = "tcsrcc-glymur",
.of_match_table = tcsr_cc_glymur_match_table,
},
};
static int __init tcsr_cc_glymur_init(void)
{
return platform_driver_register(&tcsr_cc_glymur_driver);
}
subsys_initcall(tcsr_cc_glymur_init);
static void __exit tcsr_cc_glymur_exit(void)
{
platform_driver_unregister(&tcsr_cc_glymur_driver);
}
module_exit(tcsr_cc_glymur_exit);
MODULE_DESCRIPTION("QTI TCSRCC GLYMUR Driver");
MODULE_LICENSE("GPL");

4
drivers/clk/qcom/tcsrcc-x1e80100.c
View File

@ -29,6 +29,10 @@ static struct clk_branch tcsr_edp_clkref_en = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},

2
drivers/clk/qcom/videocc-milos.c
View File

@ -366,7 +366,7 @@ static struct qcom_cc_driver_data video_cc_milos_driver_data = {
.num_clk_cbcrs = ARRAY_SIZE(video_cc_milos_critical_cbcrs),
};
static struct qcom_cc_desc video_cc_milos_desc = {
static const struct qcom_cc_desc video_cc_milos_desc = {
.config = &video_cc_milos_regmap_config,
.clks = video_cc_milos_clocks,
.num_clks = ARRAY_SIZE(video_cc_milos_clocks),

6
include/dt-bindings/clock/qcom,apss-ipq.h
View File

@ -8,5 +8,11 @@
#define APCS_ALIAS0_CLK_SRC 0
#define APCS_ALIAS0_CORE_CLK 1
#define APSS_PLL_EARLY 2
#define APSS_SILVER_CLK_SRC 3
#define APSS_SILVER_CORE_CLK 4
#define L3_PLL 5
#define L3_CLK_SRC 6
#define L3_CORE_CLK 7
#endif

4
include/dt-bindings/clock/qcom,dispcc-sc7280.h
View File

@ -52,4 +52,8 @@
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
/* DISPCC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_RSCC_BCR 1
#endif

19
include/dt-bindings/clock/qcom,gcc-msm8917.h
View File

@ -170,6 +170,23 @@
#define VFE1_CLK_SRC 163
#define VSYNC_CLK_SRC 164
#define GPLL0_SLEEP_CLK_SRC 165
/* Addtional MSM8937-specific clocks */
#define MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC 166
#define MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC 167
#define MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC 168
#define MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC 169
#define MSM8937_BYTE1_CLK_SRC 170
#define MSM8937_ESC1_CLK_SRC 171
#define MSM8937_PCLK1_CLK_SRC 172
#define MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK 173
#define MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK 174
#define MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK 175
#define MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK 176
#define MSM8937_GCC_MDSS_BYTE1_CLK 177
#define MSM8937_GCC_MDSS_ESC1_CLK 178
#define MSM8937_GCC_MDSS_PCLK1_CLK 179
#define MSM8937_GCC_OXILI_AON_CLK 180
#define MSM8937_GCC_OXILI_TIMER_CLK 181
/* GCC block resets */
#define GCC_CAMSS_MICRO_BCR 0
@ -187,5 +204,7 @@
#define VENUS_GDSC 5
#define VFE0_GDSC 6
#define VFE1_GDSC 7
/* Additional MSM8937-specific GDSCs */
#define MSM8937_OXILI_CX_GDSC 8
#endif

6
include/dt-bindings/clock/qcom,gcc-sdm660.h
View File

@ -138,10 +138,16 @@
#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
#define GCC_RX0_USB2_CLKREF_CLK 129
#define GCC_RX1_USB2_CLKREF_CLK 130
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 131
#define GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK 132
#define GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK 133
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
#define USB_30_GDSC 2
#define HLOS1_VOTE_TURING_ADSP_GDSC 3
#define HLOS2_VOTE_TURING_ADSP_GDSC 4
#define HLOS1_VOTE_LPASS_ADSP_GDSC 5
#define GCC_QUSB2PHY_PRIM_BCR 0
#define GCC_QUSB2PHY_SEC_BCR 1

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include/dt-bindings/clock/qcom,glymur-dispcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
/* DISP_CC clocks */
#define DISP_CC_ESYNC0_CLK 0
#define DISP_CC_ESYNC0_CLK_SRC 1
#define DISP_CC_ESYNC1_CLK 2
#define DISP_CC_ESYNC1_CLK_SRC 3
#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
#define DISP_CC_MDSS_AHB1_CLK 5
#define DISP_CC_MDSS_AHB_CLK 6
#define DISP_CC_MDSS_AHB_CLK_SRC 7
#define DISP_CC_MDSS_BYTE0_CLK 8
#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
#define DISP_CC_MDSS_BYTE1_CLK 12
#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_LINK_CLK 18
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK 21
#define DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 23
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 24
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 25
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 26
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 27
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28
#define DISP_CC_MDSS_DPTX1_AUX_CLK 29
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30
#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
#define DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK 34
#define DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC 35
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41
#define DISP_CC_MDSS_DPTX2_AUX_CLK 42
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_LINK_CLK 44
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 45
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 46
#define DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK 47
#define DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC 48
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 54
#define DISP_CC_MDSS_DPTX3_AUX_CLK 55
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 56
#define DISP_CC_MDSS_DPTX3_LINK_CLK 57
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59
#define DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK 60
#define DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC 61
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64
#define DISP_CC_MDSS_ESC0_CLK 65
#define DISP_CC_MDSS_ESC0_CLK_SRC 66
#define DISP_CC_MDSS_ESC1_CLK 67
#define DISP_CC_MDSS_ESC1_CLK_SRC 68
#define DISP_CC_MDSS_MDP1_CLK 69
#define DISP_CC_MDSS_MDP_CLK 70
#define DISP_CC_MDSS_MDP_CLK_SRC 71
#define DISP_CC_MDSS_MDP_LUT1_CLK 72
#define DISP_CC_MDSS_MDP_LUT_CLK 73
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 74
#define DISP_CC_MDSS_PCLK0_CLK 75
#define DISP_CC_MDSS_PCLK0_CLK_SRC 76
#define DISP_CC_MDSS_PCLK1_CLK 77
#define DISP_CC_MDSS_PCLK1_CLK_SRC 78
#define DISP_CC_MDSS_PCLK2_CLK 79
#define DISP_CC_MDSS_PCLK2_CLK_SRC 80
#define DISP_CC_MDSS_RSCC_AHB_CLK 81
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 82
#define DISP_CC_MDSS_VSYNC1_CLK 83
#define DISP_CC_MDSS_VSYNC_CLK 84
#define DISP_CC_MDSS_VSYNC_CLK_SRC 85
#define DISP_CC_OSC_CLK 86
#define DISP_CC_OSC_CLK_SRC 87
#define DISP_CC_PLL0 88
#define DISP_CC_PLL1 89
#define DISP_CC_SLEEP_CLK 90
#define DISP_CC_SLEEP_CLK_SRC 91
#define DISP_CC_XO_CLK 92
#define DISP_CC_XO_CLK_SRC 93
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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include/dt-bindings/clock/qcom,glymur-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL1 2
#define GCC_GPLL14 3
#define GCC_GPLL14_OUT_EVEN 4
#define GCC_GPLL4 5
#define GCC_GPLL5 6
#define GCC_GPLL7 7
#define GCC_GPLL8 8
#define GCC_GPLL9 9
#define GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK 10
#define GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK 11
#define GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK 12
#define GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK 13
#define GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK 14
#define GCC_AGGRE_UFS_PHY_AXI_CLK 15
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 16
#define GCC_AGGRE_USB2_PRIM_AXI_CLK 17
#define GCC_AGGRE_USB3_MP_AXI_CLK 18
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 19
#define GCC_AGGRE_USB3_SEC_AXI_CLK 20
#define GCC_AGGRE_USB3_TERT_AXI_CLK 21
#define GCC_AGGRE_USB4_0_AXI_CLK 22
#define GCC_AGGRE_USB4_1_AXI_CLK 23
#define GCC_AGGRE_USB4_2_AXI_CLK 24
#define GCC_AV1E_AHB_CLK 25
#define GCC_AV1E_AXI_CLK 26
#define GCC_AV1E_XO_CLK 27
#define GCC_BOOT_ROM_AHB_CLK 28
#define GCC_CAMERA_AHB_CLK 29
#define GCC_CAMERA_HF_AXI_CLK 30
#define GCC_CAMERA_SF_AXI_CLK 31
#define GCC_CAMERA_XO_CLK 32
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 33
#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 34
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 35
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 36
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 37
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 38
#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 39
#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 40
#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 41
#define GCC_DISP_AHB_CLK 42
#define GCC_DISP_HF_AXI_CLK 43
#define GCC_EVA_AHB_CLK 44
#define GCC_EVA_AXI0_CLK 45
#define GCC_EVA_AXI0C_CLK 46
#define GCC_EVA_XO_CLK 47
#define GCC_GP1_CLK 48
#define GCC_GP1_CLK_SRC 49
#define GCC_GP2_CLK 50
#define GCC_GP2_CLK_SRC 51
#define GCC_GP3_CLK 52
#define GCC_GP3_CLK_SRC 53
#define GCC_GPU_CFG_AHB_CLK 54
#define GCC_GPU_GEMNOC_GFX_CLK 55
#define GCC_GPU_GPLL0_CLK_SRC 56
#define GCC_GPU_GPLL0_DIV_CLK_SRC 57
#define GCC_PCIE_0_AUX_CLK 58
#define GCC_PCIE_0_AUX_CLK_SRC 59
#define GCC_PCIE_0_CFG_AHB_CLK 60
#define GCC_PCIE_0_MSTR_AXI_CLK 61
#define GCC_PCIE_0_PHY_RCHNG_CLK 62
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 63
#define GCC_PCIE_0_PIPE_CLK 64
#define GCC_PCIE_0_SLV_AXI_CLK 65
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 66
#define GCC_PCIE_1_AUX_CLK 67
#define GCC_PCIE_1_AUX_CLK_SRC 68
#define GCC_PCIE_1_CFG_AHB_CLK 69
#define GCC_PCIE_1_MSTR_AXI_CLK 70
#define GCC_PCIE_1_PHY_RCHNG_CLK 71
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
#define GCC_PCIE_1_PIPE_CLK 73
#define GCC_PCIE_1_SLV_AXI_CLK 74
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
#define GCC_PCIE_2_AUX_CLK 76
#define GCC_PCIE_2_AUX_CLK_SRC 77
#define GCC_PCIE_2_CFG_AHB_CLK 78
#define GCC_PCIE_2_MSTR_AXI_CLK 79
#define GCC_PCIE_2_PHY_RCHNG_CLK 80
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 81
#define GCC_PCIE_2_PIPE_CLK 82
#define GCC_PCIE_2_SLV_AXI_CLK 83
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 84
#define GCC_PCIE_3A_AUX_CLK 85
#define GCC_PCIE_3A_AUX_CLK_SRC 86
#define GCC_PCIE_3A_CFG_AHB_CLK 87
#define GCC_PCIE_3A_MSTR_AXI_CLK 88
#define GCC_PCIE_3A_PHY_RCHNG_CLK 89
#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 90
#define GCC_PCIE_3A_PIPE_CLK 91
#define GCC_PCIE_3A_PIPE_CLK_SRC 92
#define GCC_PCIE_3A_SLV_AXI_CLK 93
#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 94
#define GCC_PCIE_3B_AUX_CLK 95
#define GCC_PCIE_3B_AUX_CLK_SRC 96
#define GCC_PCIE_3B_CFG_AHB_CLK 97
#define GCC_PCIE_3B_MSTR_AXI_CLK 98
#define GCC_PCIE_3B_PHY_RCHNG_CLK 99
#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 100
#define GCC_PCIE_3B_PIPE_CLK 101
#define GCC_PCIE_3B_PIPE_CLK_SRC 102
#define GCC_PCIE_3B_PIPE_DIV2_CLK 103
#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 104
#define GCC_PCIE_3B_SLV_AXI_CLK 105
#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 106
#define GCC_PCIE_4_AUX_CLK 107
#define GCC_PCIE_4_AUX_CLK_SRC 108
#define GCC_PCIE_4_CFG_AHB_CLK 109
#define GCC_PCIE_4_MSTR_AXI_CLK 110
#define GCC_PCIE_4_PHY_RCHNG_CLK 111
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 112
#define GCC_PCIE_4_PIPE_CLK 113
#define GCC_PCIE_4_PIPE_CLK_SRC 114
#define GCC_PCIE_4_PIPE_DIV2_CLK 115
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 116
#define GCC_PCIE_4_SLV_AXI_CLK 117
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 118
#define GCC_PCIE_5_AUX_CLK 119
#define GCC_PCIE_5_AUX_CLK_SRC 120
#define GCC_PCIE_5_CFG_AHB_CLK 121
#define GCC_PCIE_5_MSTR_AXI_CLK 122
#define GCC_PCIE_5_PHY_RCHNG_CLK 123
#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 124
#define GCC_PCIE_5_PIPE_CLK 125
#define GCC_PCIE_5_PIPE_CLK_SRC 126
#define GCC_PCIE_5_PIPE_DIV2_CLK 127
#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 128
#define GCC_PCIE_5_SLV_AXI_CLK 129
#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 130
#define GCC_PCIE_6_AUX_CLK 131
#define GCC_PCIE_6_AUX_CLK_SRC 132
#define GCC_PCIE_6_CFG_AHB_CLK 133
#define GCC_PCIE_6_MSTR_AXI_CLK 134
#define GCC_PCIE_6_PHY_RCHNG_CLK 135
#define GCC_PCIE_6_PHY_RCHNG_CLK_SRC 136
#define GCC_PCIE_6_PIPE_CLK 137
#define GCC_PCIE_6_PIPE_CLK_SRC 138
#define GCC_PCIE_6_PIPE_DIV2_CLK 139
#define GCC_PCIE_6_PIPE_DIV_CLK_SRC 140
#define GCC_PCIE_6_SLV_AXI_CLK 141
#define GCC_PCIE_6_SLV_Q2A_AXI_CLK 142
#define GCC_PCIE_NOC_PWRCTL_CLK 143
#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 144
#define GCC_PCIE_NOC_SF_CENTER_CLK 145
#define GCC_PCIE_NOC_SLAVE_SF_EAST_CLK 146
#define GCC_PCIE_NOC_SLAVE_SF_WEST_CLK 147
#define GCC_PCIE_NOC_TSCTR_CLK 148
#define GCC_PCIE_PHY_3A_AUX_CLK 149
#define GCC_PCIE_PHY_3A_AUX_CLK_SRC 150
#define GCC_PCIE_PHY_3B_AUX_CLK 151
#define GCC_PCIE_PHY_3B_AUX_CLK_SRC 152
#define GCC_PCIE_PHY_4_AUX_CLK 153
#define GCC_PCIE_PHY_4_AUX_CLK_SRC 154
#define GCC_PCIE_PHY_5_AUX_CLK 155
#define GCC_PCIE_PHY_5_AUX_CLK_SRC 156
#define GCC_PCIE_PHY_6_AUX_CLK 157
#define GCC_PCIE_PHY_6_AUX_CLK_SRC 158
#define GCC_PCIE_RSCC_CFG_AHB_CLK 159
#define GCC_PCIE_RSCC_XO_CLK 160
#define GCC_PDM2_CLK 161
#define GCC_PDM2_CLK_SRC 162
#define GCC_PDM_AHB_CLK 163
#define GCC_PDM_XO4_CLK 164
#define GCC_QMIP_AV1E_AHB_CLK 165
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 166
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 167
#define GCC_QMIP_CAMERA_RT_AHB_CLK 168
#define GCC_QMIP_GPU_AHB_CLK 169
#define GCC_QMIP_PCIE_3A_AHB_CLK 170
#define GCC_QMIP_PCIE_3B_AHB_CLK 171
#define GCC_QMIP_PCIE_4_AHB_CLK 172
#define GCC_QMIP_PCIE_5_AHB_CLK 173
#define GCC_QMIP_PCIE_6_AHB_CLK 174
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 175
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 177
#define GCC_QMIP_VIDEO_VCODEC1_AHB_CLK 178
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 179
#define GCC_QUPV3_OOB_CORE_2X_CLK 180
#define GCC_QUPV3_OOB_CORE_CLK 181
#define GCC_QUPV3_OOB_M_AHB_CLK 182
#define GCC_QUPV3_OOB_QSPI_S0_CLK 183
#define GCC_QUPV3_OOB_QSPI_S0_CLK_SRC 184
#define GCC_QUPV3_OOB_QSPI_S1_CLK 185
#define GCC_QUPV3_OOB_QSPI_S1_CLK_SRC 186
#define GCC_QUPV3_OOB_S0_CLK 187
#define GCC_QUPV3_OOB_S0_CLK_SRC 188
#define GCC_QUPV3_OOB_S1_CLK 189
#define GCC_QUPV3_OOB_S1_CLK_SRC 190
#define GCC_QUPV3_OOB_S_AHB_CLK 191
#define GCC_QUPV3_OOB_TCXO_CLK 192
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 193
#define GCC_QUPV3_WRAP0_CORE_CLK 194
#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 195
#define GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC 196
#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 197
#define GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC 198
#define GCC_QUPV3_WRAP0_QSPI_S6_CLK 199
#define GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC 200
#define GCC_QUPV3_WRAP0_S0_CLK 201
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 202
#define GCC_QUPV3_WRAP0_S1_CLK 203
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 204
#define GCC_QUPV3_WRAP0_S2_CLK 205
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 206
#define GCC_QUPV3_WRAP0_S3_CLK 207
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 208
#define GCC_QUPV3_WRAP0_S4_CLK 209
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 210
#define GCC_QUPV3_WRAP0_S5_CLK 211
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 212
#define GCC_QUPV3_WRAP0_S6_CLK 213
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 214
#define GCC_QUPV3_WRAP0_S7_CLK 215
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 216
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 217
#define GCC_QUPV3_WRAP1_CORE_CLK 218
#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 219
#define GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC 220
#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 221
#define GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC 222
#define GCC_QUPV3_WRAP1_QSPI_S6_CLK 223
#define GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC 224
#define GCC_QUPV3_WRAP1_S0_CLK 225
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 226
#define GCC_QUPV3_WRAP1_S1_CLK 227
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 228
#define GCC_QUPV3_WRAP1_S2_CLK 229
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 230
#define GCC_QUPV3_WRAP1_S3_CLK 231
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 232
#define GCC_QUPV3_WRAP1_S4_CLK 233
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 234
#define GCC_QUPV3_WRAP1_S5_CLK 235
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 236
#define GCC_QUPV3_WRAP1_S6_CLK 237
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 238
#define GCC_QUPV3_WRAP1_S7_CLK 239
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 240
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 241
#define GCC_QUPV3_WRAP2_CORE_CLK 242
#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 243
#define GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC 244
#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 245
#define GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC 246
#define GCC_QUPV3_WRAP2_QSPI_S6_CLK 247
#define GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC 248
#define GCC_QUPV3_WRAP2_S0_CLK 249
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 250
#define GCC_QUPV3_WRAP2_S1_CLK 251
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 252
#define GCC_QUPV3_WRAP2_S2_CLK 253
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 254
#define GCC_QUPV3_WRAP2_S3_CLK 255
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 256
#define GCC_QUPV3_WRAP2_S4_CLK 257
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 258
#define GCC_QUPV3_WRAP2_S5_CLK 259
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 260
#define GCC_QUPV3_WRAP2_S6_CLK 261
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 262
#define GCC_QUPV3_WRAP2_S7_CLK 263
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 264
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 265
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 266
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 267
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 268
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 269
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 270
#define GCC_SDCC2_AHB_CLK 271
#define GCC_SDCC2_APPS_CLK 272
#define GCC_SDCC2_APPS_CLK_SRC 273
#define GCC_SDCC4_AHB_CLK 274
#define GCC_SDCC4_APPS_CLK 275
#define GCC_SDCC4_APPS_CLK_SRC 276
#define GCC_UFS_PHY_AHB_CLK 277
#define GCC_UFS_PHY_AXI_CLK 278
#define GCC_UFS_PHY_AXI_CLK_SRC 279
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 280
#define GCC_UFS_PHY_ICE_CORE_CLK 281
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 282
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 283
#define GCC_UFS_PHY_PHY_AUX_CLK 284
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 285
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 286
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 287
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 288
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 289
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 290
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 291
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 292
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 293
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 294
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 295
#define GCC_USB20_MASTER_CLK 296
#define GCC_USB20_MASTER_CLK_SRC 297
#define GCC_USB20_MOCK_UTMI_CLK 298
#define GCC_USB20_MOCK_UTMI_CLK_SRC 299
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 300
#define GCC_USB20_SLEEP_CLK 301
#define GCC_USB30_MP_MASTER_CLK 302
#define GCC_USB30_MP_MASTER_CLK_SRC 303
#define GCC_USB30_MP_MOCK_UTMI_CLK 304
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 305
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 306
#define GCC_USB30_MP_SLEEP_CLK 307
#define GCC_USB30_PRIM_MASTER_CLK 308
#define GCC_USB30_PRIM_MASTER_CLK_SRC 309
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 310
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 311
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 312
#define GCC_USB30_PRIM_SLEEP_CLK 313
#define GCC_USB30_SEC_MASTER_CLK 314
#define GCC_USB30_SEC_MASTER_CLK_SRC 315
#define GCC_USB30_SEC_MOCK_UTMI_CLK 316
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 317
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 318
#define GCC_USB30_SEC_SLEEP_CLK 319
#define GCC_USB30_TERT_MASTER_CLK 320
#define GCC_USB30_TERT_MASTER_CLK_SRC 321
#define GCC_USB30_TERT_MOCK_UTMI_CLK 322
#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 323
#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 324
#define GCC_USB30_TERT_SLEEP_CLK 325
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 326
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 327
#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 328
#define GCC_USB3_MP_PHY_AUX_CLK 329
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 330
#define GCC_USB3_MP_PHY_COM_AUX_CLK 331
#define GCC_USB3_MP_PHY_PIPE_0_CLK 332
#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 333
#define GCC_USB3_MP_PHY_PIPE_1_CLK 334
#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 335
#define GCC_USB3_PRIM_PHY_AUX_CLK 336
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 337
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 338
#define GCC_USB3_PRIM_PHY_PIPE_CLK 339
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 340
#define GCC_USB3_SEC_PHY_AUX_CLK 341
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 342
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 343
#define GCC_USB3_SEC_PHY_PIPE_CLK 344
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 345
#define GCC_USB3_TERT_PHY_AUX_CLK 346
#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 347
#define GCC_USB3_TERT_PHY_COM_AUX_CLK 348
#define GCC_USB3_TERT_PHY_PIPE_CLK 349
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 350
#define GCC_USB4_0_CFG_AHB_CLK 351
#define GCC_USB4_0_DP0_CLK 352
#define GCC_USB4_0_DP1_CLK 353
#define GCC_USB4_0_MASTER_CLK 354
#define GCC_USB4_0_MASTER_CLK_SRC 355
#define GCC_USB4_0_PHY_DP0_CLK_SRC 356
#define GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC 357
#define GCC_USB4_0_PHY_DP1_CLK_SRC 358
#define GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC 359
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 360
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 362
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 363
#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 364
#define GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC 365
#define GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC 366
#define GCC_USB4_0_PHY_RX0_CLK 367
#define GCC_USB4_0_PHY_RX0_CLK_SRC 368
#define GCC_USB4_0_PHY_RX1_CLK 369
#define GCC_USB4_0_PHY_RX1_CLK_SRC 370
#define GCC_USB4_0_PHY_SYS_CLK_SRC 371
#define GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC 372
#define GCC_USB4_0_PHY_USB_PIPE_CLK 373
#define GCC_USB4_0_SB_IF_CLK 374
#define GCC_USB4_0_SB_IF_CLK_SRC 375
#define GCC_USB4_0_SYS_CLK 376
#define GCC_USB4_0_TMU_CLK 377
#define GCC_USB4_0_TMU_CLK_SRC 378
#define GCC_USB4_0_UC_HRR_CLK 379
#define GCC_USB4_1_CFG_AHB_CLK 380
#define GCC_USB4_1_DP0_CLK 381
#define GCC_USB4_1_DP1_CLK 382
#define GCC_USB4_1_MASTER_CLK 383
#define GCC_USB4_1_MASTER_CLK_SRC 384
#define GCC_USB4_1_PHY_DP0_CLK_SRC 385
#define GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC 386
#define GCC_USB4_1_PHY_DP1_CLK_SRC 387
#define GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC 388
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 389
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 390
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 391
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 392
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 393
#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 394
#define GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC 395
#define GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC 396
#define GCC_USB4_1_PHY_RX0_CLK 397
#define GCC_USB4_1_PHY_RX0_CLK_SRC 398
#define GCC_USB4_1_PHY_RX1_CLK 399
#define GCC_USB4_1_PHY_RX1_CLK_SRC 400
#define GCC_USB4_1_PHY_SYS_CLK_SRC 401
#define GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC 402
#define GCC_USB4_1_PHY_USB_PIPE_CLK 403
#define GCC_USB4_1_SB_IF_CLK 404
#define GCC_USB4_1_SB_IF_CLK_SRC 405
#define GCC_USB4_1_SYS_CLK 406
#define GCC_USB4_1_TMU_CLK 407
#define GCC_USB4_1_TMU_CLK_SRC 408
#define GCC_USB4_1_UC_HRR_CLK 409
#define GCC_USB4_2_CFG_AHB_CLK 410
#define GCC_USB4_2_DP0_CLK 411
#define GCC_USB4_2_DP1_CLK 412
#define GCC_USB4_2_MASTER_CLK 413
#define GCC_USB4_2_MASTER_CLK_SRC 414
#define GCC_USB4_2_PHY_DP0_CLK_SRC 415
#define GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC 416
#define GCC_USB4_2_PHY_DP1_CLK_SRC 417
#define GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC 418
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 419
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 420
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 421
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 422
#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 423
#define GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC 424
#define GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC 425
#define GCC_USB4_2_PHY_RX0_CLK 426
#define GCC_USB4_2_PHY_RX0_CLK_SRC 427
#define GCC_USB4_2_PHY_RX1_CLK 428
#define GCC_USB4_2_PHY_RX1_CLK_SRC 429
#define GCC_USB4_2_PHY_SYS_CLK_SRC 430
#define GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC 431
#define GCC_USB4_2_PHY_USB_PIPE_CLK 432
#define GCC_USB4_2_SB_IF_CLK 433
#define GCC_USB4_2_SB_IF_CLK_SRC 434
#define GCC_USB4_2_SYS_CLK 435
#define GCC_USB4_2_TMU_CLK 436
#define GCC_USB4_2_TMU_CLK_SRC 437
#define GCC_USB4_2_UC_HRR_CLK 438
#define GCC_VIDEO_AHB_CLK 439
#define GCC_VIDEO_AXI0_CLK 440
#define GCC_VIDEO_AXI0C_CLK 441
#define GCC_VIDEO_AXI1_CLK 442
#define GCC_VIDEO_XO_CLK 443
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0
#define GCC_PCIE_1_TUNNEL_GDSC 1
#define GCC_PCIE_2_TUNNEL_GDSC 2
#define GCC_PCIE_3A_GDSC 3
#define GCC_PCIE_3A_PHY_GDSC 4
#define GCC_PCIE_3B_GDSC 5
#define GCC_PCIE_3B_PHY_GDSC 6
#define GCC_PCIE_4_GDSC 7
#define GCC_PCIE_4_PHY_GDSC 8
#define GCC_PCIE_5_GDSC 9
#define GCC_PCIE_5_PHY_GDSC 10
#define GCC_PCIE_6_GDSC 11
#define GCC_PCIE_6_PHY_GDSC 12
#define GCC_UFS_PHY_GDSC 13
#define GCC_USB20_PRIM_GDSC 14
#define GCC_USB30_MP_GDSC 15
#define GCC_USB30_PRIM_GDSC 16
#define GCC_USB30_SEC_GDSC 17
#define GCC_USB30_TERT_GDSC 18
#define GCC_USB3_MP_SS0_PHY_GDSC 19
#define GCC_USB3_MP_SS1_PHY_GDSC 20
#define GCC_USB4_0_GDSC 21
#define GCC_USB4_1_GDSC 22
#define GCC_USB4_2_GDSC 23
#define GCC_USB_0_PHY_GDSC 24
#define GCC_USB_1_PHY_GDSC 25
#define GCC_USB_2_PHY_GDSC 26
/* GCC resets */
#define GCC_AV1E_BCR 0
#define GCC_CAMERA_BCR 1
#define GCC_DISPLAY_BCR 2
#define GCC_EVA_BCR 3
#define GCC_GPU_BCR 4
#define GCC_PCIE_0_LINK_DOWN_BCR 5
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_0_PHY_BCR 7
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_0_TUNNEL_BCR 9
#define GCC_PCIE_1_LINK_DOWN_BCR 10
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
#define GCC_PCIE_1_PHY_BCR 12
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
#define GCC_PCIE_1_TUNNEL_BCR 14
#define GCC_PCIE_2_LINK_DOWN_BCR 15
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
#define GCC_PCIE_2_PHY_BCR 17
#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
#define GCC_PCIE_2_TUNNEL_BCR 19
#define GCC_PCIE_3A_BCR 20
#define GCC_PCIE_3A_LINK_DOWN_BCR 21
#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 22
#define GCC_PCIE_3A_PHY_BCR 23
#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 24
#define GCC_PCIE_3B_BCR 25
#define GCC_PCIE_3B_LINK_DOWN_BCR 26
#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 27
#define GCC_PCIE_3B_PHY_BCR 28
#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 29
#define GCC_PCIE_4_BCR 30
#define GCC_PCIE_4_LINK_DOWN_BCR 31
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 32
#define GCC_PCIE_4_PHY_BCR 33
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 34
#define GCC_PCIE_5_BCR 35
#define GCC_PCIE_5_LINK_DOWN_BCR 36
#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 37
#define GCC_PCIE_5_PHY_BCR 38
#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 39
#define GCC_PCIE_6_BCR 40
#define GCC_PCIE_6_LINK_DOWN_BCR 41
#define GCC_PCIE_6_NOCSR_COM_PHY_BCR 42
#define GCC_PCIE_6_PHY_BCR 43
#define GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR 44
#define GCC_PCIE_NOC_BCR 45
#define GCC_PCIE_PHY_BCR 46
#define GCC_PCIE_PHY_CFG_AHB_BCR 47
#define GCC_PCIE_PHY_COM_BCR 48
#define GCC_PCIE_RSCC_BCR 49
#define GCC_PDM_BCR 50
#define GCC_QUPV3_WRAPPER_0_BCR 51
#define GCC_QUPV3_WRAPPER_1_BCR 52
#define GCC_QUPV3_WRAPPER_2_BCR 53
#define GCC_QUPV3_WRAPPER_OOB_BCR 54
#define GCC_QUSB2PHY_HS0_MP_BCR 55
#define GCC_QUSB2PHY_HS1_MP_BCR 56
#define GCC_QUSB2PHY_PRIM_BCR 57
#define GCC_QUSB2PHY_SEC_BCR 58
#define GCC_QUSB2PHY_TERT_BCR 59
#define GCC_QUSB2PHY_USB20_HS_BCR 60
#define GCC_SDCC2_BCR 61
#define GCC_SDCC4_BCR 62
#define GCC_TCSR_PCIE_BCR 63
#define GCC_UFS_PHY_BCR 64
#define GCC_USB20_PRIM_BCR 65
#define GCC_USB30_MP_BCR 66
#define GCC_USB30_PRIM_BCR 67
#define GCC_USB30_SEC_BCR 68
#define GCC_USB30_TERT_BCR 69
#define GCC_USB3_MP_SS0_PHY_BCR 70
#define GCC_USB3_MP_SS1_PHY_BCR 71
#define GCC_USB3_PHY_PRIM_BCR 72
#define GCC_USB3_PHY_SEC_BCR 73
#define GCC_USB3_PHY_TERT_BCR 74
#define GCC_USB3_UNIPHY_MP0_BCR 75
#define GCC_USB3_UNIPHY_MP1_BCR 76
#define GCC_USB3PHY_PHY_PRIM_BCR 77
#define GCC_USB3PHY_PHY_SEC_BCR 78
#define GCC_USB3PHY_PHY_TERT_BCR 79
#define GCC_USB3UNIPHY_PHY_MP0_BCR 80
#define GCC_USB3UNIPHY_PHY_MP1_BCR 81
#define GCC_USB4_0_BCR 82
#define GCC_USB4_0_DP0_PHY_PRIM_BCR 83
#define GCC_USB4_1_BCR 84
#define GCC_USB4_2_BCR 85
#define GCC_USB_0_PHY_BCR 86
#define GCC_USB_1_PHY_BCR 87
#define GCC_USB_2_PHY_BCR 88
#define GCC_VIDEO_AXI0_CLK_ARES 89
#define GCC_VIDEO_AXI1_CLK_ARES 90
#define GCC_VIDEO_BCR 91
#endif

24
include/dt-bindings/clock/qcom,glymur-tcsr.h Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
/* TCSR_CC clocks */
#define TCSR_EDP_CLKREF_EN 0
#define TCSR_PCIE_1_CLKREF_EN 1
#define TCSR_PCIE_2_CLKREF_EN 2
#define TCSR_PCIE_3_CLKREF_EN 3
#define TCSR_PCIE_4_CLKREF_EN 4
#define TCSR_USB2_1_CLKREF_EN 5
#define TCSR_USB2_2_CLKREF_EN 6
#define TCSR_USB2_3_CLKREF_EN 7
#define TCSR_USB2_4_CLKREF_EN 8
#define TCSR_USB3_0_CLKREF_EN 9
#define TCSR_USB3_1_CLKREF_EN 10
#define TCSR_USB4_1_CLKREF_EN 11
#define TCSR_USB4_2_CLKREF_EN 12
#endif

3
include/dt-bindings/interconnect/qcom,ipq5424.h
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@ -21,4 +21,7 @@
#define MASTER_CNOC_USB 16
#define SLAVE_CNOC_USB 17
#define MASTER_CPU 0
#define SLAVE_L3 1
#endif /* INTERCONNECT_QCOM_IPQ5424_H */