github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-30 10:04:04 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amdgpu: Use SMUIO 15.0.0 offsets for TSC upper and lower count.

Browse Source 
Define and use regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 and
regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 for TSC upper and lower count.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Ramalingeswara Reddy, Kanala <Kanala.RamalingeswaraReddy@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Ramalingeswara Reddy, Kanala 2026-03-31 17:23:22 +05:30 committed by Alex Deucher
parent a094bcf204
commit 574b3b14f7
1 changed files with 26 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -64,6 +64,11 @@
#define regPC_CONFIG_CNTL_1 0x194d
#define regPC_CONFIG_CNTL_1_BASE_IDX 1
#define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 0x0030
#define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0_BASE_IDX 1
#define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 0x0031
#define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0_BASE_IDX 1
#define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
#define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
@ -5234,11 +5239,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, true);
} else {
preempt_disable();
clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
if (clock_counter_hi_pre != clock_counter_hi_after)
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
if (amdgpu_ip_version(adev, SMUIO_HWIP, 0) < IP_VERSION(15, 0, 0)) {
clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_UPPER);
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_LOWER);
clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_UPPER);
if (clock_counter_hi_pre != clock_counter_hi_after)
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_LOWER);
} else {
clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0);
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0);
clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0);
if (clock_counter_hi_pre != clock_counter_hi_after)
clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0);
}
preempt_enable();
}
clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);