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dt-bindings: soc: Add new VN-X board description based on Versal NET

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The Versal NET (Networked Adaptive Compute Acceleration Platform) from
AMD/Xilinx is a next-generation adaptive platform designed for high
performance computing, networking, and AI acceleration. It is part of the
Versal ACAP (Adaptive Compute Acceleration Platform) family.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e4486141cf9b1d36b03624cc73621b2e3bba894.1738657826.git.michal.simek@amd.com
This commit is contained in:
Shubhrajyoti Datta 2025-02-04 09:30:32 +01:00 committed by Michal Simek
parent 385a59e7f7
commit 573debf030
1 changed files with 9 additions and 2 deletions
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11
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
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@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@amd.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
description:
AMD/Xilinx boards with ARM 32/64bits cores
properties:
$nodename:
@ -187,6 +187,13 @@ properties:
- const: qemu,mbv
- const: amd,mbv
- description: Xilinx Versal NET VN-X revA platform
items:
enum:
- xlnx,versal-net-vnx-revA
- xlnx,versal-net-vnx
- xlnx,versal-net
additionalProperties: true
...