clk: qcom: Constify qcom_cc_driver_data

The static 'struct qcom_cc_driver_data' contains probe match-like data
and is not modified: neither by the driver defining it nor by common.c
code using it.

Make it const for code safety and code readability.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331091721.61613-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-03-31 11:17:22 +02:00 committed by Bjorn Andersson
parent 03aa6ed706
commit 573ddd0d22
33 changed files with 33 additions and 33 deletions

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@ -211,7 +211,7 @@ static struct clk_alpha_pll *ipa5424_apss_plls[] = {
&ipq5424_apss_pll,
};
static struct qcom_cc_driver_data ipa5424_apss_driver_data = {
static const struct qcom_cc_driver_data ipa5424_apss_driver_data = {
.alpha_plls = ipa5424_apss_plls,
.num_alpha_plls = ARRAY_SIZE(ipa5424_apss_plls),
};

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@ -395,7 +395,7 @@ static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
.alpha_plls = cam_bist_mclk_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls),
.clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs,

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@ -414,7 +414,7 @@ static const struct regmap_config cam_bist_mclk_cc_sm8750_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
static const struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,

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@ -2615,7 +2615,7 @@ static const struct regmap_config cam_cc_kaanapali_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
.alpha_plls = cam_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_kaanapali_plls),
.clk_cbcrs = cam_cc_kaanapali_critical_cbcrs,

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@ -2117,7 +2117,7 @@ static const struct regmap_config cam_cc_milos_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_milos_driver_data = {
static const struct qcom_cc_driver_data cam_cc_milos_driver_data = {
.alpha_plls = cam_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls),
.clk_cbcrs = cam_cc_milos_critical_cbcrs,

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@ -1556,7 +1556,7 @@ static const struct regmap_config cam_cc_qcs615_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
static const struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
.alpha_plls = cam_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_qcs615_plls),
};

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@ -2842,7 +2842,7 @@ static const struct regmap_config cam_cc_sc8180x_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
static const struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
.alpha_plls = cam_cc_sc8180x_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sc8180x_plls),
.clk_cbcrs = cam_cc_sc8180x_critical_cbcrs,

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@ -3030,7 +3030,7 @@ static struct gdsc *cam_cc_sm8450_gdscs[] = {
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
static const struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
.alpha_plls = cam_cc_sm8450_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls),
.clk_cbcrs = cam_cc_sm8450_critical_cbcrs,

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@ -3530,7 +3530,7 @@ static const struct regmap_config cam_cc_sm8550_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
static const struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
.alpha_plls = cam_cc_sm8550_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
.clk_cbcrs = cam_cc_sm8550_critical_cbcrs,

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@ -3548,7 +3548,7 @@ static const struct regmap_config cam_cc_sm8650_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
static const struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
.alpha_plls = cam_cc_sm8650_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8650_plls),
.clk_cbcrs = cam_cc_sm8650_critical_cbcrs,

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@ -2666,7 +2666,7 @@ static const struct regmap_config cam_cc_sm8750_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
static const struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
.alpha_plls = cam_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8750_plls),
.clk_cbcrs = cam_cc_sm8750_critical_cbcrs,

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@ -2447,7 +2447,7 @@ static const struct regmap_config cam_cc_x1e80100_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
static const struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
.alpha_plls = cam_cc_x1e80100_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls),
.clk_cbcrs = cam_cc_x1e80100_critical_cbcrs,

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@ -49,7 +49,7 @@ struct qcom_cc_desc {
size_t num_icc_hws;
unsigned int icc_first_node_id;
bool use_rpm;
struct qcom_cc_driver_data *driver_data;
const struct qcom_cc_driver_data *driver_data;
};
/**

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@ -2076,7 +2076,7 @@ static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));
}
static struct qcom_cc_driver_data disp_cc_eliza_driver_data = {
static const struct qcom_cc_driver_data disp_cc_eliza_driver_data = {
.alpha_plls = disp_cc_eliza_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_eliza_plls),
.clk_cbcrs = disp_cc_eliza_critical_cbcrs,

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@ -1934,7 +1934,7 @@ static const struct regmap_config disp_cc_glymur_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
static const struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
.alpha_plls = disp_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_glymur_plls),
.clk_cbcrs = disp_cc_glymur_critical_cbcrs,

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@ -1907,7 +1907,7 @@ static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regm
regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4));
}
static struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
.alpha_plls = disp_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_kaanapali_plls),
.clk_cbcrs = disp_cc_kaanapali_critical_cbcrs,

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@ -926,7 +926,7 @@ static void disp_cc_milos_clk_regs_configure(struct device *dev, struct regmap *
}
static struct qcom_cc_driver_data disp_cc_milos_driver_data = {
static const struct qcom_cc_driver_data disp_cc_milos_driver_data = {
.alpha_plls = disp_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_milos_plls),
.clk_cbcrs = disp_cc_milos_critical_cbcrs,

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@ -751,7 +751,7 @@ static const struct regmap_config disp_cc_qcs615_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
static const struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
.alpha_plls = disp_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_qcs615_plls),
.clk_cbcrs = disp_cc_qcs615_critical_cbcrs,

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@ -3051,7 +3051,7 @@ static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
}
static struct qcom_cc_driver_data gcc_eliza_driver_data = {
static const struct qcom_cc_driver_data gcc_eliza_driver_data = {
.clk_cbcrs = gcc_eliza_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs),
.dfs_rcgs = gcc_eliza_dfs_clocks,

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@ -8561,7 +8561,7 @@ static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
static struct qcom_cc_driver_data gcc_glymur_driver_data = {
static const struct qcom_cc_driver_data gcc_glymur_driver_data = {
.clk_cbcrs = gcc_glymur_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,

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@ -3485,7 +3485,7 @@ static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regm
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
static struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
.clk_cbcrs = gcc_kaanapali_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_kaanapali_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,

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@ -3171,7 +3171,7 @@ static const struct regmap_config gcc_milos_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data gcc_milos_driver_data = {
static const struct qcom_cc_driver_data gcc_milos_driver_data = {
.clk_cbcrs = gcc_milos_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_milos_critical_cbcrs),
.dfs_rcgs = gcc_milos_dfs_clocks,

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@ -4675,7 +4675,7 @@ static void clk_sc8180x_regs_configure(struct device *dev, struct regmap *regmap
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
}
static struct qcom_cc_driver_data gcc_sc8180x_driver_data = {
static const struct qcom_cc_driver_data gcc_sc8180x_driver_data = {
.clk_cbcrs = gcc_sc8180x_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc8180x_critical_cbcrs),
.dfs_rcgs = gcc_sc8180x_dfs_clocks,

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@ -574,7 +574,7 @@ static const struct regmap_config gpu_cc_glymur_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data gpu_cc_glymur_driver_data = {
static const struct qcom_cc_driver_data gpu_cc_glymur_driver_data = {
.alpha_plls = gpu_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls),
.clk_cbcrs = gpu_cc_glymur_critical_cbcrs,

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@ -437,7 +437,7 @@ static const struct regmap_config gpu_cc_kaanapali_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
.alpha_plls = gpu_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_kaanapali_plls),
.clk_cbcrs = gpu_cc_kaanapali_critical_cbcrs,

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@ -518,7 +518,7 @@ static const struct regmap_config gpu_cc_milos_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
static const struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
.alpha_plls = gpu_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_milos_plls),
.clk_cbcrs = gpu_cc_milos_critical_cbcrs,

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@ -485,7 +485,7 @@ static void clk_qcs615_regs_crc_configure(struct device *dev, struct regmap *reg
regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000);
}
static struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
static const struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
.alpha_plls = gpu_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcs615_plls),
.clk_cbcrs = gpu_cc_qcs615_critical_cbcrs,

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@ -487,7 +487,7 @@ static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
}
static struct qcom_cc_driver_data video_cc_glymur_driver_data = {
static const struct qcom_cc_driver_data video_cc_glymur_driver_data = {
.alpha_plls = video_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls),
.clk_cbcrs = video_cc_glymur_critical_cbcrs,

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@ -776,7 +776,7 @@ static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regm
regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);
}
static struct qcom_cc_driver_data video_cc_kaanapali_driver_data = {
static const struct qcom_cc_driver_data video_cc_kaanapali_driver_data = {
.alpha_plls = video_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_kaanapali_plls),
.clk_cbcrs = video_cc_kaanapali_critical_cbcrs,

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@ -359,7 +359,7 @@ static const struct regmap_config video_cc_milos_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_milos_driver_data = {
static const struct qcom_cc_driver_data video_cc_milos_driver_data = {
.alpha_plls = video_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_milos_plls),
.clk_cbcrs = video_cc_milos_critical_cbcrs,

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@ -295,7 +295,7 @@ static const struct regmap_config video_cc_qcs615_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_qcs615_driver_data = {
static const struct qcom_cc_driver_data video_cc_qcs615_driver_data = {
.alpha_plls = video_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_qcs615_plls),
.clk_cbcrs = video_cc_qcs615_critical_cbcrs,

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@ -427,7 +427,7 @@ static const struct regmap_config video_cc_sm8450_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_sm8450_driver_data = {
static const struct qcom_cc_driver_data video_cc_sm8450_driver_data = {
.alpha_plls = video_cc_sm8450_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_sm8450_plls),
.clk_cbcrs = video_cc_sm8450_critical_cbcrs,

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@ -407,7 +407,7 @@ static void clk_sm8750_regs_configure(struct device *dev, struct regmap *regmap)
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
}
static struct qcom_cc_driver_data video_cc_sm8750_driver_data = {
static const struct qcom_cc_driver_data video_cc_sm8750_driver_data = {
.alpha_plls = video_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_sm8750_plls),
.clk_cbcrs = video_cc_sm8750_critical_cbcrs,