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arm64: errata: Factor out broken AMU const counter cap
Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites. Signed-off-by: Beata Michalska <beata.michalska@arm.com> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
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@ -1040,9 +1040,17 @@ config ARM64_ERRATUM_1902691
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If unsure, say Y.
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config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
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bool
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# Targeting errata affecting AMEVCNTR01, the AMU constant counter.
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# On affected CPUs the counter may not increment at the expected rate,
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# making it unreliable. As a result, AMU users should treat it as
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# unavailable rather than relying on misleading counter values.
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config ARM64_ERRATUM_2457168
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bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
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depends on ARM64_AMU_EXTN
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select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 2457168.
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@ -384,6 +384,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
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static const struct midr_range workaround_amu_constcnt_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2457168
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/* Cortex-A510 r0p0-r1p1 */
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MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
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#endif
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{}
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};
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#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */
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#ifdef CONFIG_CAVIUM_ERRATUM_23154
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static const struct midr_range cavium_erratum_23154_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_THUNDERX),
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@ -919,14 +929,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2457168
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#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
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{
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.desc = "ARM erratum 2457168",
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.capability = ARM64_WORKAROUND_2457168,
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.desc = "Broken AMU AMEVCNTR01 (const counter)",
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.capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT,
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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/* Cortex-A510 r0p0-r1p1 */
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CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
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CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2038923
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@ -2089,7 +2089,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
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cpumask_set_cpu(smp_processor_id(), &amu_cpus);
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/* 0 reference values signal broken/disabled counters */
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if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
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if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT))
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update_freq_counters_refs();
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}
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}
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@ -400,7 +400,7 @@ static void cpu_read_constcnt(void *val)
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* the counter is disabled. A return value of 0 at counter read is
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* properly handled as an error case by the users of the counter.
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*/
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*(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ?
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*(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ?
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0UL : read_constcnt();
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}
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@ -461,8 +461,9 @@ static void amu_read_core_const_ctrs(void *val)
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/*
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* cpu_read_constcnt() incurs slight latency due to the
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* ARM64_WORKAROUND_2457168 check. Read it first to minimize
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* the sampling skew between the const and core counters.
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* ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT check.
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* Read it first to minimize the sampling skew between the const
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* and core counters.
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*/
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cpu_read_constcnt(&ctrs->constcnt);
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cpu_read_corecnt(&ctrs->corecnt);
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@ -105,7 +105,6 @@ WORKAROUND_1902691
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WORKAROUND_2038923
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WORKAROUND_2064142
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WORKAROUND_2077057
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WORKAROUND_2457168
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WORKAROUND_2645198
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WORKAROUND_2658417
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WORKAROUND_4193714
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@ -132,3 +131,4 @@ WORKAROUND_REPEAT_TLBI_SYNC
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WORKAROUND_SPECULATIVE_AT
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WORKAROUND_SPECULATIVE_SSBS
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WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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WORKAROUND_BROKEN_AMU_CONSTCNT
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