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arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
Add initial device tree support for the Qualcomm IPQ5018 SoC and rdp432-c2 board. Few things like 'reboot' does not work because, couple of more 'SCM' APIS are needed to clear some TrustZone settings. Those will be posted separately. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Sricharan Ramabadhran
Bjorn Andersson
parent
f810050479
commit
570006756a
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@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
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72
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
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72
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* IPQ5018 MP03.1-C2 board device tree source
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*
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* Copyright (c) 2023 The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include "ipq5018.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
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compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
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aliases {
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serial0 = &blsp1_uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&blsp1_uart1 {
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pinctrl-0 = <&uart1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhc_1 {
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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max-frequency = <192000000>;
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bus-width = <4>;
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&tlmm {
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio9";
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function = "sdc1_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio8";
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function = "sdc1_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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function = "sdc1_data";
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drive-strength = <8>;
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bias-disable;
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};
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};
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};
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&xo_board_clk {
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clock-frequency = <24000000>;
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};
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250
arch/arm64/boot/dts/qcom/ipq5018.dtsi
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250
arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@ -0,0 +1,250 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* IPQ5018 SoC device tree source
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*
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* Copyright (c) 2023 The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-unified;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq5018", "qcom,scm";
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};
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};
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memory@40000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x40000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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tz_region: tz@4ac00000 {
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reg = <0x0 0x4ac00000 0x0 0x200000>;
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no-map;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 47>;
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interrupt-controller;
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#interrupt-cells = <2>;
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uart1_pins: uart1-state {
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pins = "gpio31", "gpio32", "gpio33", "gpio34";
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function = "blsp1_uart1";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq5018";
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reg = <0x01800000 0x80000>;
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clocks = <&xo_board_clk>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000>;
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reg-names = "hc";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board_clk>;
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clock-names = "iface", "core", "xo";
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non-removable;
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status = "disabled";
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x0b000000 0x1000>, /* GICD */
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<0x0b002000 0x2000>, /* GICC */
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<0x0b001000 0x1000>, /* GICH */
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<0x0b004000 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0b00a000 0x1ffa>;
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v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00000000 0xff8>;
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msi-controller;
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};
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v2m1: v2m@1000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00001000 0xff8>;
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msi-controller;
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};
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};
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timer@b120000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@b120000 {
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <0>;
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};
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frame@b123000 {
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reg = <0xb123000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <1>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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reg = <0x0b125000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@b126000 {
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reg = <0x0b126000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@b127000 {
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reg = <0x0b127000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@b128000 {
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reg = <0x0b128000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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