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arm64: zynqmp: Wire qspi on multiple boards

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Couple of boards have qspi on the board that's why enable controller and
describe them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2021-06-14 17:25:33 +02:00
parent f4be206cd1
commit 56e5460151
9 changed files with 121 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -19,6 +19,7 @@ / {
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
@ -36,6 +37,19 @@ &dcc {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&sata {
status = "okay";
/* SATA OOB timing settings */

16
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2019, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -20,6 +20,7 @@ / {
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
@ -37,6 +38,19 @@ &dcc {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&uart0 {
status = "okay";
};

14
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View File

@ -26,6 +26,7 @@ aliases {
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
};
chosen {
@ -339,6 +340,19 @@ conf {
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};

14
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View File

@ -26,6 +26,7 @@ aliases {
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;
};
chosen {
@ -161,6 +162,19 @@ &i2c1 {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};

15
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View File

@ -30,6 +30,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
};
chosen {
@ -934,6 +935,20 @@ &psgtr {
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};

14
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View File

@ -28,6 +28,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
};
chosen {
@ -427,6 +428,19 @@ &psgtr {
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&sata {
status = "okay";
/* SATA OOB timing settings */

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View File

@ -28,6 +28,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
};
chosen {
@ -435,6 +436,9 @@ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};

15
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View File

@ -30,6 +30,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
};
chosen {
@ -928,6 +929,20 @@ &psgtr {
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};

15
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View File

@ -29,6 +29,7 @@ aliases {
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
@ -772,6 +773,20 @@ &psgtr {
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};