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arm64: dts: qcom: sm8650: add iris DT node

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Add DT entries for the sm8650 iris decoder.

Since the firmware is required to be signed, only enable
on Qualcomm development boards where the firmware is
available.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250613-topic-sm8x50-upstream-iris-8650-dt-v4-1-35ea7952f2d2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong 2025-06-13 10:41:06 +02:00 committed by Bjorn Andersson
parent 79b896e7da
commit 56cf5ad39a
4 changed files with 105 additions and 0 deletions
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4
arch/arm64/boot/dts/qcom/sm8650-hdk.dts
View File

@ -894,6 +894,10 @@ &ipa {
status = "okay";
};
&iris {
status = "okay";
};
&gpu {
status = "okay";

4
arch/arm64/boot/dts/qcom/sm8650-mtp.dts
View File

@ -585,6 +585,10 @@ vreg_l7n_3p3: ldo7 {
};
};
&iris {
status = "okay";
};
&lpass_tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio21";

4
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
View File

@ -824,6 +824,10 @@ &ipa {
status = "okay";
};
&iris {
status = "okay";
};
&gpu {
status = "okay";

93
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -4962,6 +4962,99 @@ opp-202000000 {
};
};
iris: video-codec@aa00000 {
compatible = "qcom,sm8650-iris";
reg = <0 0x0aa00000 0 0xf0000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
<&videocc VIDEO_CC_MVS0_GDSC>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
power-domain-names = "venus",
"vcodec0",
"mxc",
"mmcx";
operating-points-v2 = <&iris_opp_table>;
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
clock-names = "iface",
"core",
"vcodec0_core";
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";
memory-region = <&video_mem>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&videocc VIDEO_CC_XO_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "bus",
"xo",
"core";
iommus = <&apps_smmu 0x1940 0>,
<&apps_smmu 0x1947 0>;
dma-coherent;
/*
* IRIS firmware is signed by vendors, only
* enable in boards where the proper signed firmware
* is available.
*/
status = "disabled";
iris_opp_table: opp-table {
compatible = "operating-points-v2";
opp-196000000 {
opp-hz = /bits/ 64 <196000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_low_svs_d1>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};
opp-435000000 {
opp-hz = /bits/ 64 <435000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_nom>;
};
opp-533333334 {
opp-hz = /bits/ 64 <533333334>;
required-opps = <&rpmhpd_opp_turbo>,
<&rpmhpd_opp_turbo>;
};
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8650-videocc";
reg = <0 0x0aaf0000 0 0x10000>;