github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 17:13:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/xe: use entry_dump callbacks for xe2+ PAT dumps

Browse Source 
Move xe2+ PAT entry printing into the entry_dump op so platform
specific logic stays localized, simplifying future maintenance.

v2:
 - Do not null xe->pat.ops for VFs.
 - Skip PAT init and dump on VFs (-EOPNOTSUPP), avoiding NULL ops use.

v3:
 - fixed typo

v4: (Matt)
 - Switch xe2_dump() to use the new ops->entry_dump() vfunc.
 - Remove xe3p_xpc_dump() and reuse the common xe2_dump() for Xe3p XPC.
 - This also fixes Xe3p_HPM media PAT dumping by using the proper
non-MCR access for the PAT register range (bspec 76445).

Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Brian Nguyen <brian3.nguyen@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260130175349.2249033-1-x.wang@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Xin Wang 2026-01-30 17:53:49 +00:00 committed by Matt Roper
parent f89dbe14a0
commit 568d9d0d83
1 changed files with 16 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
drivers/gpu/drm/xe/xe_pat.c
View File

@ -88,6 +88,7 @@ struct xe_pat_ops {
void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[],
int n_entries);
int (*dump)(struct xe_gt *gt, struct drm_printer *p);
void (*entry_dump)(struct drm_printer *p, const char *label, u32 pat, bool rsvd);
};
static const struct xe_pat_table_entry xelp_pat_table[] = {
@ -458,7 +459,7 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p)
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
xe_pat_index_label(label, sizeof(label), i);
xe2_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid);
}
/*
@ -471,7 +472,7 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p)
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
drm_printf(p, "Page Table Access:\n");
xe2_pat_entry_dump(p, "PTA_MODE", pat, false);
xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);
return 0;
}
@ -480,44 +481,14 @@ static const struct xe_pat_ops xe2_pat_ops = {
.program_graphics = program_pat_mcr,
.program_media = program_pat,
.dump = xe2_dump,
.entry_dump = xe2_pat_entry_dump,
};
static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
u32 pat;
int i;
char label[PAT_LABEL_LEN];
CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
if (!fw_ref.domains)
return -ETIMEDOUT;
drm_printf(p, "PAT table: (* = reserved entry)\n");
for (i = 0; i < xe->pat.n_entries; i++) {
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
xe_pat_index_label(label, sizeof(label), i);
xe3p_xpc_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
}
/*
* Also print PTA_MODE, which describes how the hardware accesses
* PPGTT entries.
*/
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
drm_printf(p, "Page Table Access:\n");
xe3p_xpc_pat_entry_dump(p, "PTA_MODE", pat, false);
return 0;
}
static const struct xe_pat_ops xe3p_xpc_pat_ops = {
.program_graphics = program_pat_mcr,
.program_media = program_pat,
.dump = xe3p_xpc_dump,
.dump = xe2_dump,
.entry_dump = xe3p_xpc_pat_entry_dump,
};
void xe_pat_init_early(struct xe_device *xe)
@ -600,20 +571,17 @@ void xe_pat_init_early(struct xe_device *xe)
GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);
}
/* VFs can't program nor dump PAT settings */
if (IS_SRIOV_VF(xe))
xe->pat.ops = NULL;
xe_assert(xe, !xe->pat.ops || xe->pat.ops->dump);
xe_assert(xe, !xe->pat.ops || xe->pat.ops->program_graphics);
xe_assert(xe, !xe->pat.ops || MEDIA_VER(xe) < 13 || xe->pat.ops->program_media);
xe_assert(xe, xe->pat.ops->dump);
xe_assert(xe, xe->pat.ops->program_graphics);
xe_assert(xe, MEDIA_VER(xe) < 13 || xe->pat.ops->program_media);
xe_assert(xe, GRAPHICS_VER(xe) < 20 || xe->pat.ops->entry_dump);
}
void xe_pat_init(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
if (!xe->pat.ops)
if (IS_SRIOV_VF(xe))
return;
if (xe_gt_is_media_type(gt))
@ -633,7 +601,7 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
if (!xe->pat.ops)
if (IS_SRIOV_VF(xe))
return -EOPNOTSUPP;
return xe->pat.ops->dump(gt, p);
@ -658,12 +626,9 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
for (u32 i = 0; i < xe->pat.n_entries; i++) {
u32 pat = xe->pat.table[i].value;
if (GRAPHICS_VERx100(xe) == 3511) {
if (GRAPHICS_VER(xe) >= 20) {
xe_pat_index_label(label, sizeof(label), i);
xe3p_xpc_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
xe_pat_index_label(label, sizeof(label), i);
xe2_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid);
} else if (xe->info.platform == XE_METEORLAKE) {
xelpg_pat_entry_dump(p, i, pat);
} else if (xe->info.platform == XE_PVC) {
@ -679,14 +644,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
u32 pat = xe->pat.pat_pta->value;
drm_printf(p, "Page Table Access:\n");
xe2_pat_entry_dump(p, "PTA_MODE", pat, false);
xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);
}
if (xe->pat.pat_ats) {
u32 pat = xe->pat.pat_ats->value;
drm_printf(p, "PCIe ATS/PASID:\n");
xe2_pat_entry_dump(p, "PAT_ATS ", pat, false);
xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false);
}
drm_printf(p, "Cache Level:\n");