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drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ

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DRM_AMDGPU_NAVI3X_USERQ config support is not required for
usermode queue.

v2: rebase.

Cc: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Arvind Yadav <Arvind.Yadav@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Arvind Yadav 2025-04-22 19:29:03 +05:30 committed by Alex Deucher
parent 716ad3c28f
commit 56801cb83c
10 changed files with 4 additions and 56 deletions
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8
drivers/gpu/drm/amd/amdgpu/Kconfig
View File

@ -96,14 +96,6 @@ config DRM_AMDGPU_WERROR
Add -Werror to the build flags for amdgpu.ko.
Only enable this if you are warning code for amdgpu.ko.
config DRM_AMDGPU_NAVI3X_USERQ
bool "Enable amdgpu usermode queues"
depends on DRM_AMDGPU
default n
help
Choose this option to enable GFX usermode queue support for GFX/SDMA/Compute
workload submission. This feature is experimental and supported on GFX11+.
source "drivers/gpu/drm/amd/acp/Kconfig"
source "drivers/gpu/drm/amd/display/Kconfig"
source "drivers/gpu/drm/amd/amdkfd/Kconfig"

2
drivers/gpu/drm/amd/amdgpu/Makefile
View File

@ -177,7 +177,7 @@ amdgpu-y += \
mes_v12_0.o \
# add GFX userqueue support
amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_userqueue.o
amdgpu-y += mes_userqueue.o
# add UVD block
amdgpu-y += \

7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -3513,9 +3513,7 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
amdgpu_amdkfd_suspend(adev, false);
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_suspend(adev);
#endif
/* Workaround for ASICs need to disable SMC first */
amdgpu_device_smu_fini_early(adev);
@ -5086,9 +5084,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
if (!adev->in_s0ix) {
amdgpu_amdkfd_suspend(adev, adev->in_runpm);
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_suspend(adev);
#endif
}
r = amdgpu_device_evict_resources(adev);
@ -5156,11 +5152,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)
r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
if (r)
goto exit;
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
r = amdgpu_userq_resume(adev);
if (r)
goto exit;
#endif
}
r = amdgpu_device_ip_late_init(adev);

5
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View File

@ -1981,9 +1981,7 @@ static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx,
if (adev->gfx.userq_sch_req_count[idx] == 0) {
cancel_delayed_work_sync(&adev->gfx.enforce_isolation[idx].work);
if (!adev->gfx.userq_sch_inactive[idx]) {
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_stop_sched_for_enforce_isolation(adev, idx);
#endif
if (adev->kfd.init_complete)
amdgpu_amdkfd_stop_sched(adev, idx);
adev->gfx.userq_sch_inactive[idx] = true;
@ -2041,9 +2039,8 @@ void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work)
/* Tell KFD to resume the runqueue */
WARN_ON_ONCE(!adev->gfx.userq_sch_inactive[idx]);
WARN_ON_ONCE(adev->gfx.userq_sch_req_count[idx]);
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_start_sched_for_enforce_isolation(adev, idx);
#endif
if (adev->kfd.init_complete)
amdgpu_amdkfd_start_sched(adev, idx);
adev->gfx.userq_sch_inactive[idx] = false;

8
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
View File

@ -129,7 +129,6 @@ amdgpu_userq_active(struct amdgpu_userq_mgr *uq_mgr)
return ret;
}
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
static struct amdgpu_usermode_queue *
amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid)
{
@ -520,13 +519,6 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data,
return r;
}
#else
int amdgpu_userq_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
return -ENOTSUPP;
}
#endif
static int
amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr)

18
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
View File

@ -216,7 +216,6 @@ void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv)
kref_put(&fence_drv->refcount, amdgpu_userq_fence_driver_destroy);
}
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence)
{
*userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC);
@ -288,7 +287,6 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq,
return 0;
}
#endif
static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f)
{
@ -343,7 +341,6 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops = {
.release = amdgpu_userq_fence_release,
};
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/**
* amdgpu_userq_fence_read_wptr - Read the userq wptr value
*
@ -594,15 +591,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
return r;
}
#else
int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
return -ENOTSUPP;
}
#endif
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
@ -968,10 +957,3 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
return r;
}
#else
int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
return -ENOTSUPP;
}
#endif

4
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -1606,7 +1606,6 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
if (!adev->gfx.disable_uq &&
adev->gfx.me_fw_version >= 2390 &&
adev->gfx.pfp_fw_version >= 2530 &&
@ -1615,7 +1614,6 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
#endif
break;
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 4):
@ -1623,13 +1621,11 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 5, 1):
case IP_VERSION(11, 5, 2):
case IP_VERSION(11, 5, 3):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->gfx.disable_uq) {
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
#endif
break;
default:
break;

2
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View File

@ -1416,7 +1416,6 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
if (!adev->gfx.disable_uq &&
adev->gfx.me_fw_version >= 2780 &&
adev->gfx.pfp_fw_version >= 2840 &&
@ -1425,7 +1424,6 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
#endif
break;
default:
break;

3
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
View File

@ -1363,11 +1363,10 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
else
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif
r = amdgpu_sdma_sysfs_reset_mask_init(adev);
if (r)
return r;

3
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
View File

@ -1338,12 +1338,9 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
else
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif
return r;
}