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drm/tyr: Use register! macro for JOB_CONTROL

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Define the JOB_CONTROL register block with the kernel's register! macro
and replace the existing hand-written JOB IRQ register definitions with
typed register and field accessors.

This adds typed definitions for the raw status, clear, mask, and status
registers, including the per-CSG interrupt bits and the global interface
interrupt bit.

This reduces open-coded bit manipulation, keeps the JOB_CONTROL register
layout in one place, and makes the definitions easier to read and
maintain.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Co-developed-by: Daniel Almeida <daniel.almeida@collabora.com>
Signed-off-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Link: https://patch.msgid.link/20260409-b4-tyr-use-register-macro-v5-v5-3-8abfff8a0204@collabora.com
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
This commit is contained in:
Deborah Brouwer 2026-04-09 10:51:26 -07:00 committed by Alice Ryhl
parent b00d6a7398
commit 566eec206a
1 changed files with 50 additions and 8 deletions
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58
drivers/gpu/drm/tyr/regs.rs
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@ -28,7 +28,6 @@
#![allow(dead_code)]
use kernel::{
bits::bit_u32,
device::{
Bound,
Device, //
@ -894,14 +893,57 @@ fn from(status: McuStatus) -> Self {
}
}
pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register;
pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register;
pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register;
pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register;
pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31);
pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register;
pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register;
pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register;
pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register;
/// These registers correspond to the JOB_CONTROL register page.
/// They are involved in communication between the firmware running on the MCU and the host.
pub(crate) mod job_control {
use kernel::register;
register! {
/// Raw status of job interrupts.
///
/// Write to this register to trigger these interrupts.
/// Writing a 1 to a bit forces that bit on.
pub(crate) JOB_IRQ_RAWSTAT(u32) @ 0x1000 {
/// CSG request. These bits indicate that CSGn requires attention from the host.
30:0 csg;
/// GLB request. Indicates that the GLB interface requires attention from the host.
31:31 glb => bool;
}
/// Clear job interrupts. Write only.
///
/// Write a 1 to a bit to clear the corresponding bit in [`JOB_IRQ_RAWSTAT`].
pub(crate) JOB_IRQ_CLEAR(u32) @ 0x1004 {
/// Clear CSG request interrupts.
30:0 csg;
/// Clear GLB request interrupt.
31:31 glb => bool;
}
/// Mask for job interrupts.
///
/// Set each bit to 1 to enable the corresponding interrupt source or to 0 to disable it.
pub(crate) JOB_IRQ_MASK(u32) @ 0x1008 {
/// Enable CSG request interrupts.
30:0 csg;
/// Enable GLB request interrupt.
31:31 glb => bool;
}
/// Active job interrupts. Read only.
///
/// This register contains the result of ANDing together [`JOB_IRQ_RAWSTAT`] and
/// [`JOB_IRQ_MASK`].
pub(crate) JOB_IRQ_STATUS(u32) @ 0x100c {
/// CSG request interrupt status.
30:0 csg;
/// GLB request interrupt status.
31:31 glb => bool;
}
}
}